DESCRIPTION

Field of the invention

The present invention relates to a digital di f ferential ampli fier with ultra-low power consumption for continuous quantities , in particular for loT applications and/or biosensors .

Description of the prior art

The development of energetically autonomous Internet of Things ( ToT ) nodes and latest-generation remotely-powered biosensors with submillimetre dimensions requires the integrated circuits interfacing with such ultra-compact sensors to have special characteristics and performance . In particular, it is necessary that such circuits provide performance levels which can be configured according to the available energy and which can operate on ultra-low supply voltages , which are very often inaccurately controlled and extremely variable , such as those that can be obtained, for example , from ultraminiaturi zed energy harvesters . The reali zation of interface circuits having such characteristics is particularly problematical for sensors outputting continuous quantities and/or whenever the level of accuracy required by the application is so high as to greatly limit the actual feasibility in many fields of application . In recent years , a number of interface circuits for ultra-compact sensors capable of operating at low supply voltages and with ultralow power consumption (<10nW) [ 1-2 ] have been developed for audio and biosignal acquisition ( in particular, electrocardiogram, ECG) applications. In such solutions, however, reference is always made to a sensor coupled to the interface through a capacitor (i.e. in alternating current) . The acquisition of signals with a direct- current component, as is necessary, for example, to acquire temperature sensors and electro-chemical sensors, is more problematical and, de facto, the level of accuracy in direct current required by these applications is obtained, according to the state of the art, by using chopping and auto-zeroing techniques, at the cost of significant power consumption (>lpW) , high area occupation (mm ² ) , and low input impedance.

The Applicant observes that the above-mentioned limitations make such approaches unsuitable for loT and/or biosensor applications.

Brief description of the invention

It is therefore the object of the present invention to provide a differential amplifier which can overcome the above-described drawbacks .

In accordance with a first aspect, the invention relates to a differential amplifier.

Preferably, the amplifier comprises an input section.

Preferably, the input section is configured for receiving a first voltage and a second voltage.

Preferably, a difference between the first voltage and the second voltage is equal to a differential voltage.

Preferably, the amplifier comprises an output block.

Preferably, the output block is configured for generating an output voltage representative of said differential voltage.

Preferably, the amplifier comprises a compensation block.

Preferably, the compensation block is configured for generating a common-mode compensation voltage. Preferably, the ampli fier comprises an adder block .

Preferably, the adder block is configured for adding to each one of said first and second voltages a common-mode compensation voltage , thereby obtaining a first compensated voltage and a second compensated voltage , respectively .

Preferably, the ampli fier comprises a comparator block .

Preferably, the comparator block is configured for making a first comparison between the first compensated voltage and a preset threshold .

Preferably, the comparator block is configured for making a second comparison between the second compensated voltage and said preset threshold .

Preferably, the ampli fier comprises a control block .

Preferably, the control block is associated with said comparator block .

Preferably, i f the first compensated voltage is above the preset threshold and the second compensated voltage is below the preset threshold, the control block is configured for controlling said output block to increase the output voltage by a predetermined quantity .

Preferably, i f the first compensated voltage is below the preset threshold and the second compensated voltage is above the preset threshold, the control block is configured for controlling said output block to decrease the output voltage by a predetermined quantity .

Preferably, i f the first compensated voltage is above the preset threshold and the second compensated voltage is above the preset threshold, the control block is configured for controlling the compensation block to decrease the common-mode compensation voltage by a predetermined quantity . Preferably, i f the first compensated voltage is below the preset threshold and the second compensated voltage is below the preset threshold, the control block is configured for controlling the compensation block to increase the common-mode compensation voltage by a predetermined quantity .

The invention may comprise one or more of the following preferred features .

Preferably, said comparator block is configured for making said first comparison and said second comparison at di f ferent time instants .

Preferably, said comparator block is configured for making said first comparison prior to said second comparison, or for making said second comparison prior to said first comparison .

Preferably, said comparator block is reali zed as a logic port in CMOS technology .

Preferably, in said output block, the output voltage is incremented/decremented by means of a mechanism of charge redistribution between two capacitors having signi ficantly di f ferent capacities .

Preferably, in said compensation block, the common-mode compensation voltage is incremented/decremented by means of a mechanism of charge redistribution between two capacitors having signi ficantly di f ferent capacities .

Preferably, said comparator block and said control block form a finite-state machine .

Brief description of the drawings

The invention will become more apparent in light of the following detailed description, provided herein merely by way of non-limiting example , wherein reference will be made to the annexed drawings , wherein : - Figure 1 shows a basic diagram of an amplifier in accordance with the present invention;

- Figure 2 schematically shows some operating phases of the amplifier of Figure 1;

- Figures 3a-3d schematically show some possible operating situations of the amplifier of Figure 1;

- Figure 4 shows one possible circuit implementation of the amplifier of Figure 1;

- Figure 5 shows one possible use of the amplifier of Figure 1 in a closed-loop configuration;

- Figure 6 shows a functional description of the amplifier of Figure 1 used in the configuration shown in Figure 5;

- Figure 7 shows a state transition diagram representative of the operation of the amplifier of Figure 1;

- Figures 8a-8h show some operating states of the amplifier of Figure 1, with reference to the diagram of Figure 7;

- Figures 9-11, 12a-12e and 13a-13c show some experimental implementation tests of the amplifier of Figure 1.

Detailed description of the preferred embodiments

With reference to the annexed drawings, numeral 1 designates as a whole a differential amplifier in accordance with the present invention .

On a general level, the amplifier 1 comprises an input section 10, for receiving a first voltage v+ and a second voltage v- . The input section 10 may also be configured for sampling, preferably simultaneously, the first voltage v+ and the second voltage v- .

The first and second voltages v+, v- are such that a difference between them is equal to a differential voltage vd, according to the relation vd = v+ - v-

The amplifier 1 further comprises an output block 60 configured for generating an output voltage vout representative of the differential voltage vd.

The amplifier 1 can be used in any closed-loop configuration, as known in the literature (e.g. : Sergio Franco, "Design With Operational Amplifiers And Analog Integrated Circuits" , 4th edition (2014) , McGraw Hill, New York) , and particularly for conditioning and digitally converting analogue signals of voltage and/or current and/or other electric quantities coming from ultra-compact sensors like, for example, those used in latest-generation biosensors.

In one embodiment, the output block 60 is implemented as at least one integrated capacitor, preferably having a value in the range of 1 pF to 100 pF.

The amplifier 1 further comprises a compensation block 20 configured for generating a common-mode compensation voltage vccm.

The amplifier 1 further comprises an adder block 30, connected to the input block 10 and to the compensation block 20.

The adder block 30 is configured for adding the common-mode compensation voltage vccm to the first and second voltages v+, v- . A respective first compensated voltage vA and a respective second compensated voltage vB are thus obtained.

The amplifier 1 further comprises a comparator block 40, connected downstream of the adder block 30.

The comparator block 40 is configured for making a first comparison between the first compensated voltage vA and a preset threshold VT . For example, the preset threshold VT may, for simplicity's sake, be set to zero. Other threshold values may nevertheless be used. The comparator block 40 is further configured for making a second comparison between the second compensated voltage vB and said preset threshold VT .

In other words , the comparator block 40 makes it possible to veri fy whether the first compensated voltage vA is above or below the preset threshold VT , and whether the second compensated voltage vB is above or below the preset threshold VT .

It should be noted that the comparator block 40 has an input terminal , and said input terminal receives , at distinct instants , the first compensated voltage vA and the second compensated voltage vB . In other words , the first compensated voltage vA and the second compensated voltage vB are supplied to the same input terminal of the comparator block 40 .

The first and second compensated voltages vA, vB are then processed by the same hardware components that constitute the comparator block 40 . Thus , the first compensated voltage vA is processed in much the same manner as the second compensated voltage vB . In particular, as aforesaid, the first compensated voltage vA is supplied to the input terminal of the comparator block 40 at a first instant or time interval , and the second compensated voltage vB is supplied to the input terminal of the comparator block 40 at a second instant or time interval . The second time instant or time interval is distinct and separate from the first time instant or time interval .

In one embodiment , a SAB switch is used ( Figure 1 ) , interposed between the input section 10 and the comparator block 40 , more particularly between the input section 10 and the compensation block 30 . Depending on the position, i . e . "A" or "B" , of the SAB switch, either the f irst or the second voltage v+ , v- will be added to the common-mode compensation voltage vccm, resulting in the respective first or second compensated voltage vA, vB, which will then be inputted to the comparator block 40 .

In other words , the SAB switch can be driven between a first operating condition (position "A" ) , in which it supplies the first voltage v+ to the compensation block 30 , and a second operating condition (position "B" ) , in which it supplies the second voltage v- to the compensation block 30 .

Thus , when the SAB switch is in the first operating condition, the input terminal of the comparator block 40 will receive the first compensated voltage vA; when the SAB switch SAB is in the second operating condition, the input terminal of the comparator block 40 will receive the second compensated voltage vB .

In one embodiment , the comparator block 40 is configured for making the first comparison and the second comparison at di f ferent time instants , particularly for making the first comparison prior to the second comparison .

The comparator block 40 generates digital outputs , i . e . the values of the Boolean variables D ^(A) , D ^{( B )} .

Preferably, the comparator block 40 is reali zed as a logic port ( logic buf fer ) in CMOS technology .

The ampli fier 1 comprises a control block 50 , connected downstream of the comparator block 40 and active upon the output block 60 and/or the compensation block 20 .

The control block 50 provides digital control over the output voltage vout and the common-mode compensation voltage vccm; in particular, as a function of the values of the Boolean variables D ^(A) , D ^{( B )} determined by the comparator block 40 , the control block 50 will increment/decrement the output voltage vout or the common-mode compensation voltage vccm by one unit step upon every processing interaction . In more detail : i f the first compensated voltage vA is above the preset threshold VT and the second compensated voltage vB is below the preset threshold VT , then the control block 50 will control the output block 60 to increase the output voltage vout by a predetermined quantity (unit step ) ; i f the first compensated voltage vA is below the preset threshold VT and the second compensated voltage vB is above the preset threshold VT , then the control block 50 will control the output block 60 to decrease the output voltage vout by a predetermined quantity (unit step ) ; i f the first compensated voltage vA is above the preset threshold VT and the second compensated voltage vB is above the preset threshold VT , then the control block will control the compensation block 20 to decrease the common-mode compensation voltage vccm by a predetermined quantity (unit step ) ; i f the first compensated voltage vA is below the preset threshold VT and the second compensated voltage vB is below the preset threshold VT , then the control block 50 will control the compensation block 20 to increase the common-mode compensation voltage (vccm) by a predetermined quantity (unit step ) .

In brief , in the two former cases the control block 50 acts upon the output block 60 to increase/decrease the output voltage vout , whereas in the third and fourth cases the control block 50 acts upon the compensation block 20 to decrease/ increase the common-mode compensation voltage vccm .

In one embodiment , the comparator block 40 and the control block 50 form a finite-state machine , which will be further described hereinafter . The technique executed by the amplifier 1 can be defined as a time- multiplexed digital differential amplification technique.

Preferably, only one single-ended comparator is employed (i.e. said comparator block 40) , which can be implemented even just as a simple logic port.

As aforementioned, the comparator block 40 is used at different time instants in order to compare the first voltage v+ (non-inverting input) and the second voltage v- (inverting input) of the differential structure with the same switching threshold.

Based on the results of such two comparisons, which can be expressed in terms of Boolean variables D ^(A) and D ^(B) , either the output voltage vout or the common-mode compensation voltage vccm will be updated. In more detail, from a logic viewpoint, the operation of the circuit consists of four phases, which are diagrammatically represented in their time succession in Figure 2: during the first phase (Pl) , the first and second voltages v+, v- are sampled simultaneously; during the second phase (P2) , the SAB switch is in position A (see Figure 1) and connects the capacitor charged with the first voltage v+ in series with the common mode vccm compensation block 20 and with the input of the comparator block 40, so that the input voltage of the comparator block 40 will be, in this phase, vA = v+ + vCCM. The previously mentioned adder block 30 is implemented through the connections between the SAB switch and the compensation block vccm. The logic output of the comparator, which may be either in the high state ("1") , if vA>VT, or in the low state ("0") , if vA<VT, is stored into the Boolean variable D ^(A > in the control block 50.

During the third phase (P3) , the SAB switch switches into position B, the input of the comparator block 40 is vB = v- + vCCM, and the corresponding logic output is stored into the Boolean variable D ^(B) . During the fourth phase (P4) , either the output voltage vout or the common-mode compensation voltage vccm is updated on the basis of the logic values of D ^(A) and D ^(B) .

In more detail, the following logic is executed:

- if D ^(A) = 1 and D ^(B) =0 (Figure 3a) , then the differential voltage vd = v+ - v- is greater than zero; therefore, the output voltage vout is incremented by one unit step (e.g. as in a differential amplifier with integrative characteristic) , while the commonmode compensation voltage vccm is left unchanged;

- if D ^(A) = 0 and D ^(B) =1 (Figure 3b) , then the differential voltage vd = v+ - v- is less than zero; therefore, the output voltage vout is decremented by one unit step, while the common-mode compensation voltage vccm is left unchanged;

- if D ^(A) = 1 and D ^(B) = 1 (Figure 3c) , since it is not possible to infer the sign of the differential voltage vd, the output voltage vout is left unchanged, while the common-mode compensation voltage vccm is decremented by one unit step. In this manner, the value of the common-mode compensation voltage vccm is made to approach the input common-mode voltage vcm, as required to obtain discordant logic values of D ^(A) and D ^(B) in the subsequent cycles; this will result in a tendency to fall within either one of the above-mentioned first or second cases, wherein the circuit behaves as a differential amplifier;

- if D ^(A) =0 and D ^(B) = 0 (Figure 3d) , also in this case it is not possible to infer the sign of the differential voltage vd; therefore, the output voltage vout is left unchanged, while the common-mode compensation voltage vccm is incremented by one unit step. The considerations made in regard to the preceding case apply to this case as well. The Applicant observes that, since the operation of this circuit is neither based on absolute values of the circuit elements (resistance values, capacity values, dimensions of the MOS, BJT transistors, etc.) nor based on the fact that some of these elements must be identical, it is intrinsically robust and independent of fabrication tolerances .

In particular, in one embodiment the amplifier 1 can be implemented in CMOS technology by using switched capacitors, as schematically shown in Figure 4. The comparation block 40 can be implemented as a simple CMOS logic buffer, and the switches are implemented as bootstrap pass-gates.

The output block 60 and the compensation block 20 can be provided by voltage generators, e.g. implemented as integrated capacitors C _L and C _C M having a capacity of the order of picofarads, e.g. in the range of IpF to lOOpF.

The logic functionality of the circuit is provided through a finite- state machine, which is essentially formed by the comparator block 40 and the control block 50.

Figure 7 shows the state transition diagram of said finite-state machine. To each state corresponds one of the switches' configurations shown in Figures 8a-8h.

In the state A, the input capacitor Ci _n , _P , pre-charged to the voltage of the non-inverting input v+ during the previous phase, is connected in series with C _C M and with the input of the buffer. The logic output of the latter is then stored into the flip-flop D ^(A >) at the next clock beat.

In the state B, the input capacitor Ci _n , _M , pre-charged to the voltage of the inverting input v- , is connected in series with C _C M and with the input of the buffer. The logic output of the latter is then stored into the flip-flop D ^(B) . Based on the logic values of D ^(A) and D ^(B) , the finite-state machine evolves towards either the states C+/C- or the states E+/E-.

In the states C+/C-, the capacitor Co, out is pre-charged and, in the subsequent state D, the output voltage vout across the capacitor C _L (connected in parallel with the capacitor Co, out) is updated.

In the states E+/E-, the capacitor Co, cm is pre-charged and, in the subsequent state F, the voltage vccm across the capacitor C _C M (connected in parallel with the capacitor Co, cm) is updated.

Figures 8a-8d show a first sequence of states that may be entered by the amplifier 1 in operation.

In Figure 8a (state A) , the value of vA is above the preset threshold VT, hence the Boolean variable D ^(A ) takes the value of 1.

In Figure 8b (state B) , the value of vB is below the preset threshold VT, hence the Boolean variable D ^(B > takes the value of 0.

Figures 8a-8b represent, therefore, the situation diagrammatically illustrated in Figure 3a.

In this situation:

- in the expression vA = vd/ 2 + v _cm + vccm >0, the contribution of vd/ 2 is prevailing;

- in the expression vB = -vd/2 + v _cm + vccm <0, the contribution of -vd/2 is prevailing.

The state C+ (Figure 8c) is thus determined as the next state, in which the capacitor Co, out is pre-charged to a voltage equal to V _DD /2, so that in the state D (Figure 8d) such charge is transferred to the capacitor C _L , incrementing the output voltage vout by one unit step. If vA had been below the preset threshold VT (D ^(A) = 0 ) and vB had been above the preset threshold VT (D ^(B) = 1) , as schematized in Figure 3b, the machine would have switched into the state C- , the capacitor Co, out would have been pre-charged to a voltage equal to -V _DD /2, and the output voltage vout across the capacitor C _L would have been decreased by one unit step (state D) .

Figures 8e-8h show a second sequence of states that may be entered by the amplifier 1 in operation.

In Figure 8e (state A) , the value of vA is above the preset threshold VT, hence the Boolean variable D ^(A > takes the value of 1.

In Figure 8f (state B) , the value of vB is above the preset threshold VT, hence the Boolean variable D ^(B > takes the value of 1.

Figures 8e-8f represent, therefore, the situation diagrammatically illustrated in Figure 3c.

In this situation:

- in the expression vA = vd/ 2 + v _cm + vccm >0, the contribution of (v _cm + vccm) is prevailing;

- in the expression vB = -vd/2 + v _cm + vccm <0, the contribution of (v _cm + vccm) is prevailing.

The state E- (Figure 8g) is thus determined as the next state, in which the capacitor Co, CM is pre-charged to a voltage equal to -V _DD /2, so that in the state F (Figure 8h) such charge is transferred to the capacitor C _C M, decrementing the common-mode compensation voltage vccm by one unit step.

If vA had been below the preset threshold VT (D ^(A) = 0 ) and vB had been below the preset threshold VT (D ^(B) = 0) , as schematized in Figure 3c, the machine would have switched into the state E+, the capacitor Co, CM would have been pre-charged to a voltage equal to V _DD /2, and the common-mode compensation voltage vccm across the capacitor C _C M would have been increased by one unit step (state F) .

As aforesaid, in order to increment (or decrement) the output voltage vout by one unit step, in the state C+ (or C-) , the capacitor Co, OU , whose capacity is of the order of femtofarads, e.g. in the range of IfF to lOOfF (therefore, much smaller than C _L , which is of the order of picofarads, e.g. in the range of IpF to lOOpF) , is pre-charged to the positive supply voltage V _DD /2 (or the negative supply voltage -V _DD /2) . The capacitor Co, OU is then connected in parallel with C _L in the next state D, so that, following the charge redistribution between the two capacitors, the voltage of the capacitor C _L will be incremented (or decremented) . In other words, preferably, in the output block 60 the output voltage vout can be incremented/decremented by means of a mechanism of charge redistribution between two capacitors (as aforesaid, C ₀ ,OU and C _L ) having significantly different capacities (Co, OU having a capacity of the order of fF, and C _L having a capacity of the order of pF) . In the same state D, the voltages of the inputs v+ and v- are sampled for the subsequent cycle.

In a similar manner, in the states E+ (E-) , the capacitor Co, CM, whose capacity is of the order of femtofarads, e.g. in the range of IfF to lOOfF (therefore, much smaller than the capacitor C _C M, which is of the order of picofarads, e.g. in the range of IpF to lOOpF) , is pre-charged to the positive supply voltage V _DD /2 (or the negative supply voltage -V _DD /2) and then connected in parallel with C _C M in the next state F, so as to update vccm to compensate for not only the common-mode component of the input, but also any drift or fluctuation in the logic threshold voltage of the buffer due to process variations, supply voltage and temperature. In other words, preferably, in the compensation block 20 the common-mode compensation voltage vccm can be incremented/decremented by means of a mechanism of charge redistribution between two capacitors (as aforesaid, Co, CM and C _C M) having significantly different capacities (Co, CM having a capacity of the order of fF, and C _C M having a capacity of the order of pF) . In the state F, as in the state D, the voltages of the inputs v+ and v- are sampled for the subsequent cycle. The states D or F end the operating cycle and are followed by the state A of the next cycle.

The above-described circuit operates as a digital differential amplifier with a band-gain product which is proportional to the clock frequency. Furthermore, when used in a closed-loop configuration (negative feedback) with a fixed load (Figure 5) , the digital signal corresponding to the sequence of states provides directly a digital version of the output voltage, which can be reconstructed during a post-processing phase using digital filtering techniques (Figure 6) . In addition to conceiving the invention on a theoretical level, the Applicant also carried out a series of experimental tests that confirmed the technical quality of the invention.

In more detail, the invention was validated by fabricating a test chip in 180nm CMOS technology (microphotograph in Figure 9) . The silicon area occupied by the prototype is as small as 0.00945mm ² . According to tests conducted at a temperature of 25°C and with different supply voltages (Figure 10) , the acquisition circuit based on the amplifier of the invention can operate with a variable power supply ranging from 0.2V to IV, with the maximum range of rail-to- rail input and output voltages and at clock frequencies ranging from 28kHz (at 0.2V) to 15MHz (at IV, limited by the band of the analogue pads used for the measurement) , corresponding to a band-gain product configurable from 70Hz to 40kHz. Power consumption varies from 600pW @ 0.2V to 9.58pW @ IV at the maximum clock frequency, and from 2nW @ 0.25V to 1.77pW @ IV at a clock frequency set to 50kHz.

With reference to the characterization of the circuit supplied with 0.4V, at a clock frequency of 50kHz, the band-gain product is 120Hz and the power consumption is 4.5nW. Based on static characterization tests conducted on six specimens of the fabricated device (Figure 11) , the input offset voltage varies from -188 to 230pV, the open- loop gain varies from 36.3 to 42.7dB, the common-mode rejection ratio (CMRR) varies from 60 to 74dB, and the power supply rejection ratio (PSRR) varies from 54 to 83.9dB. The input impedance is always greater than 1GQ.

Based on the characterization under dynamic conditions of the specimen #2 configured as voltage follower, the waveforms of the input and output voltages for sinusoidal input (0.1Hz, 360mVpkpk) and square wave are shown in Figures 12a-12b. The spectrum corresponding to the output for sinusoidal input shown in Figure 12d reveals a total harmonic distortion (THD) of less than 1.3%. The small-signal open-loop voltage amplification is shown in Figure 12c, resulting in a direct-current gain of 39.9dB and a band-gain product of 120Hz. The input noise power spectral density is shown in Figure 12e and has an in-band value of 1.03pV/ Hz (Figure 12e) , with a noise suppression of 1/f. The total in-band rms noise is 11.3pVrms.

Figures 13a-13b show the results of the dynamic characterization referring to the signals reconstructed starting from the digital output: in more detail, Figure 13a concerns an output for sinusoidal input, and Figure 13b shows the spectrum thereof.

The signal was reconstructed starting from the digital output for sinusoidal input (50mV peak) , after appropriate post-processing. The results reveal an SFDR of 46.5dB, a THD of -45dB and an SNDR of 43.4 dB, corresponding to an equivalent resolution (ENOB) of 6.9 bits. Figure 13c shows the acquisition of an electrocardiographic signal (ECG) , which confirms the applicability of the approach proposed herein to the acquisition of biomedical signals.

The results shown herein confirm that the circuit offers a level of performance which is similar to that of sensor-based signal acquisition front-ends currently known in the literature; compared with the latter, however, the invention is characterized by lower power consumption, minimal voltage, a wider range of supply voltages and much smaller area occupation, and is therefore particularly suitable for use in loT applications and latest-generation biomedical sensors .