Title:
DIGITAL FILTER CIRCUIT AND DIGITAL FILTER CONTROL METHOD
Document Type and Number:
WIPO Patent Application WO/2012/086262
Kind Code:
A1
Abstract:
[Objective] To provide a digital filter circuit and a digital filter control method capable of reducing circuit scale and power consumption for filter processing in the frequency domain of the overlap FDE method. [Solution] The digital filter circuit of the present invention is provided with: overlap addition means for causing a block comprising N units of data to overlap with M units of data of the previous block; FFT means for transforming a generated block using FFT processing; filter computation means for performing filter processing for the transformed block; IFFT means for transforming the block that has been subject to filter processing using IFFT processing; overlap removal means for removing M units of data from both ends of the transformed block; and clock generation means for setting the frequency of a filter processing clock signal which drives the output unit of the overlap addition means, the FFT means, the filter computation means, the IFFT means, and the input unit of the overlap removal means on the basis of the value of M.
Inventors:
SHIBAYAMA ATSUFUMI (JP)
Application Number:
PCT/JP2011/069098
Publication Date:
June 28, 2012
Filing Date:
August 18, 2011
Export Citation:
Assignee:
NEC CORP (JP)
SHIBAYAMA ATSUFUMI (JP)
SHIBAYAMA ATSUFUMI (JP)
International Classes:
H03H17/02
Foreign References:
| JP2010232857A | 2010-10-14 | |||
| JPH0823262A | 1996-01-23 | |||
| JP2006304192A | 2006-11-02 | |||
| JP2010130355A | 2010-06-10 | |||
| JP2007201523A | 2007-08-09 | |||
| JPH09135151A | 1997-05-20 | |||
| JP2010284137A | 2010-12-21 |
Other References:
See also references of EP 2658124A4
Attorney, Agent or Firm:
SHIMOSAKA, NAOKI (JP)
Naoki Shimosaka (JP)
Naoki Shimosaka (JP)
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Claims: