MODULATION (AM-PM) COMPENSATION

TECHNICAL FIELD

The present disclosure relates to wireless communications, and in particular, to a digital phase locked loop configured to compensate for amplitude-to-phase (AM-PM) variations.

BACKGROUND

The Third Generation Partnership Project (3GPP) has developed and is developing standards for Fourth Generation (4G) (also referred to as Long Term Evolution (LTE)) and Fifth Generation (5G) (also referred to as New Radio (NR)) wireless communication systems. Such systems provide, among other features, broadband communication between network nodes, such as base stations, and mobile wireless devices (WD), as well as communication between network nodes and between WDs.

Power amplifiers (PAs) are inherently nonlinear, and even more so when they are operating with high efficiency. Therefore, a PA that is efficient must be linearized to achieve a target error vector magnitude (EVM) and to avoid a high adjacent channel leakage ratio (ACLR). Typically, linearization of the PA is performed by a digital predistortion (DPD) to compensate for both amplitude-to-amplitude variations (AM-AM) and amplitude-to-phase variations (AM-PM) caused by nonlinear memory effects of the PA. But other simpler methods also exist. For example, one method involves linearization of AM-AM by deploying adaptive biasing of the PA with the envelope of the input signal. In addition, methods for compensating for AM-PM also exist.

The accuracy by which the local oscillator signal in a transmitter of a radio transceiver maintains a specific frequency affects the ability of the radio interface to avoid adjacent channel interference and other deleterious effects. Traditionally, analog phase locked loops (PLLs) have been used to provide an accurate oscillator signal, but digital PLLs are also employed. A digital PLL avoids an analog loop filter with large area capacitors, and may support advanced digital algorithms to speed up frequency hops, for example. An analog PLL on the other hand is much less complex to design and may have a better phase noise performance. For instance, at very high frequencies or for very low power, the simplicity of an analog PLL may be preferred. However, an analog PLL does not enable use of digital algorithms to achieve AM-PM phase compensation. Further, due to improvements in semiconductor technology when it comes to performance and chip area of digital circuit functions, there is a strong trend towards digital PLLs.

A digital pre-distorter (DPD) for pre-distorting a signal input to a power amplifier adds complexity and cost of both analog and digital hardware. A DPD also consumes power, thereby reducing the overall system efficiency. An in-band DPD operates only on the same frequency bandwidth, or channel as that of the transmitted signal and can typically improve EVM, but has little effect on reducing the adjacent channel leakage ratio (ACLR). To significantly reduce ACLR, the DPD must operate with higher bandwidth, typically three times the bandwidth of the channel or more. The analog hardware of the transmitter must be able to process the higher DPD frequency bandwidth, including the digital to analog converters (DACs). This leads to increased power consumption and design complexity. In addition, the DPD also provides gain expansion to counteract gain compression of the PA, which also increases complexity and power consumption. In conclusion, linearization using a DPD comes at a high cost.

SUMMARY

Linearization of AM-AM by analog methods in the PA can be effective, at least for modulation bandwidths targeted for 5G, whereas existing analog AM-PM mitigation techniques are not.

Some embodiments advantageously provide methods and radio interfaces for digital phase locked loop compensation of amplitude-to-phase (AM-PM) variations in order to reduce AM-PM distortion caused by nonlinearities of the PA. For a transmitter already using a digital PLL, no new analog hardware is needed. Signal processing to achieve the AM-PM compensation as disclosed herein may be carried out in the digital domain, using the digital IQ-signals as an input to the PLL. Some embodiments include modulating a local oscillator output signal of a digital PLL with the inverse of the phase modulation caused by AM-PM distortion of the PA. In some embodiments, the AM-PM compensation is achieved so that effect of the AM-PM is driven toward zero.

According to one aspect, a radio interface is configured to compensate for amplitude to phase, AM-PM, variations. The radio interface includes a phase-locked loop, PLL, comprising: a digitally controlled oscillator, DCO, configured to generate a local oscillator signal based at least in part on a sum of a frequency control word and an AM-PM compensation signal; a phase detector configured to detect a phase deviation of the local oscillator signal; and a loop filter configured to filter a phase error signal to produce the frequency control word, the phase error signal being determined by subtracting a phase adjustment signal from the detected phase deviation, the phase adjustment signal being based at least in part on a counteracting phase modulation to counteract AM-PM variations. The radio interface also includes processing circuitry in communication with the PLL, the processing circuitry configured to: detect an envelope of an input signal received by a transmit chain of the radio interface; map the envelope of the input signal to obtain the counteracting phase modulation; and determine the AM-PM compensation signal based at least in part on differentiation of the counteracting phase modulation.

According to this aspect, in some embodiments, the processing circuitry is configured to determine the phase adjustment signal by at least one of scaling and delaying the counteracting phase modulation and then subtracting the phase adjustment signal from the detected phase deviation of the local oscillator signal. In some embodiments, an amount of delay is based at least in part on at least one of a delay associated with the differentiation, and a delay associated with a response time of the DCO and the phase detector. In some embodiments, the AM-PM compensation signal is determined based at least in part on scaling the differentiated counteracting phase modulation. In some embodiments, an amount of the scaling is predetermined to minimize the phase error signal. In some embodiments, the processing circuitry is configured in a calibration mode to determine an amount of the scaling based at least in part on correlating the phase error signal at an input of the loop filter with the phase adjustment signal, and adjusting the scaling to drive the correlation toward zero. In some embodiments, the processing circuitry is configured in a calibration mode to determine an amount of the scaling based at least in part on: locking the PLL at each of a plurality of frequencies, and for each frequency at which the PLL is locked, storing the frequency control word. In some embodiments, the processing circuitry is configured to curve-fit to obtain a function describing the frequency control characteristic of the DCO, and using the function for the DCO frequency control characteristic when determining the scaling factor when operating at different center frequencies and frequency deviations. In some embodiments, the mapping is based at least in part on an inverse of the phase modulation arising from the nonlinearity of the power amplifier. In some embodiments, the mapping is stored in a lookup table that relates envelope values to corresponding phase deviations. In some embodiments, the mapping is based at least in part on a predetermined AM-PM characteristic of the power amplifier. In some embodiments, the mapping is nonlinear. In some embodiments, the nonlinearity is determined by curve fitting. According to another aspect, a method in a radio interface configured to compensate for amplitude to phase, AM-PM, variations is provided. The method includes generating, via digitally controlled oscillator, DCO, of a phase-locked loop, PLL, a local oscillator signal based at least in part on a sum of a frequency control word and an AM-PM compensation signal. The method also includes detecting, via a phase detector of the PLL, a phase deviation of the local oscillator signal. The method further includes filtering, via a loop filter of the PLL, a phase error signal to produce the frequency control word, the phase error signal being determined by subtracting a phase adjustment signal from the detected phase deviation, the phase adjustment signal being based at least in part on a counteracting phase modulation to counteract AM-PM variations. The method also includes detecting, via an envelope detector, an envelope of an input signal received by a transmit chain of the radio interface; mapping, via a mapping unit, the envelope of the input signal to obtain the counteracting phase modulation; and determining, via a differentiation and scaling unit, the AM-PM compensation signal based at least in part on differentiation of the counteracting phase modulation.

According to this aspect, in some embodiments, the process includes determining the phase adjustment signal by at least one of scaling and delaying the counteracting phase modulation and then subtracting the phase adjustment signal from the detected phase deviation of the local oscillator signal. In some embodiments, an amount of delay is based at least in part on at least one of a delay associated with the differentiation, and a delay associated with a response time of the DCO and the phase detector. In some embodiments, the AM-PM compensation signal is determined based at least in part on scaling the differentiated counteracting phase modulation. In some embodiments, an amount of the scaling is predetermined to minimize the phase error signal. In some embodiments, the method also includes, in a calibration mode, determining an amount of the scaling based at least in part on correlating the phase error signal with the phase adjustment signal, and adjusting the scaling to drive the correlation toward zero. In some embodiments, the method includes, in a calibration mode, determining an amount of the scaling based at least in part on: locking the PLL at each of a plurality of frequencies, and for each frequency at which the PLL is locked, storing the frequency control word. In some embodiments, the process also includes curve-fitting to obtain a function describing the frequency control characteristic of the DCO, and using the function for the DCO frequency control characteristic when determining the scaling factor when operating at different center frequencies and frequency deviations. In some embodiments, the mapping is based at least in part on an inverse of the phase modulation arising from the non-linearity of the power amplifier. In some embodiments, the mapping is stored in a lookup table that relates envelope values to corresponding phase deviations. In some embodiments, the mapping is based at least in part on a predetermined AM-PM characteristic of the power amplifier. In some embodiments, the mapping is nonlinear. In some embodiments, the nonlinearity is determined by curve fitting.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete understanding of the present embodiments, and the attendant advantages and features thereof, will be more readily understood by reference to the following detailed description when considered in conjunction with the accompanying drawings wherein:

FIG. l is a schematic diagram of an example network architecture illustrating a communication system according to principles disclosed herein;

FIG. 2 is a block diagram of a network node in communication with a wireless device over a wireless connection according to some embodiments of the present disclosure;

FIG. 3 is a simplified block diagram of processing circuitry to compensate for AM- PM distortion according to principles disclosed herein;

FIG. 4 is a more detailed block diagram of a radio interface constructed according to principles set forth herein;

FIG. 5 is a flowchart of an example process in a network node to compensate for AM- PM distortion according to principles disclosed herein;

FIG. 6 is a plot of an AM-PM characteristic of an example power amplifier to which the compensation methods disclosed herein may be applied;

FIG. 7 is an example time domain envelope signal generated by a modulated IQ signal;

FIG. 8 is an example of an estimate of phase deviations due to AM-PM introduced by a PA; and

FIG. 9 is an example frequency modulation for compensating phase deviations according to methods disclosed herein.

DETAILED DESCRIPTION

Before describing in detail example embodiments, it is noted that the embodiments reside primarily in combinations of apparatus components and processing steps related to digital phase locked loop compensation for amplitude-to-phase (AM-PM) variations. Accordingly, components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.

As used herein, relational terms, such as “first” and “second,” “top” and “bottom,” and the like, may be used solely to distinguish one entity or element from another entity or element without necessarily requiring or implying any physical or logical relationship or order between such entities or elements. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the concepts described herein. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In embodiments described herein, the joining term, “in communication with” and the like, may be used to indicate electrical or data communication, which may be accomplished by physical contact, induction, electromagnetic radiation, radio signaling, infrared signaling or optical signaling, for example. One having ordinary skill in the art will appreciate that multiple components may interoperate and modifications and variations are possible of achieving the electrical and data communication.

In some embodiments described herein, the term “coupled,” “connected,” and the like, may be used herein to indicate a connection, although not necessarily directly, and may include wired and/or wireless connections.

The term “network node” used herein can be any kind of network node comprised in a radio network which may further comprise any of base station (BS), radio base station, base transceiver station (BTS), base station controller (BSC), radio network controller (RNC), g Node B (gNB), evolved Node B (eNB or eNodeB), Node B, multi-standard radio (MSR) radio node such as MSR BS, multi-cell/multicast coordination entity (MCE), relay node, donor node controlling relay, radio access point (AP), transmission points, transmission nodes, Remote Radio Unit (RRU) Remote Radio Head (RRH), a core network node (e.g., mobile management entity (MME), self-organizing network (SON) node, a coordinating node, positioning node, MDT node, etc.), an external node (e.g., 3rd party node, a node external to the current network), nodes in distributed antenna system (DAS), a spectrum access system (SAS) node, an element management system (EMS), etc. The network node may also comprise test equipment. The term “radio node” used herein may be used to also denote a wireless device (WD) such as a wireless device (WD) or a radio network node.

In some embodiments, the non-limiting terms wireless device (WD) or a user equipment (UE) are used interchangeably. The WD herein can be any type of wireless device capable of communicating with a network node or another WD over radio signals, such as wireless device (WD). The WD may also be a radio communication device, target device, device to device (D2D) WD, machine type WD or WD capable of machine to machine communication (M2M), low-cost and/or low-complexity WD, a sensor equipped with WD, Tablet, mobile terminals, smart phone, laptop embedded equipped (LEE), laptop mounted equipment (LME), USB dongles, Customer Premises Equipment (CPE), an Internet of Things (loT) device, or a Narrowband loT (NB-IOT) device etc.

Also, in some embodiments the generic term “radio network node” is used. It can be any kind of a radio network node which may comprise any of base station, radio base station, base transceiver station, base station controller, network controller, RNC, evolved Node B (eNB), Node B, gNB, Multi-cell/multicast Coordination Entity (MCE), relay node, access point, radio access point, Remote Radio Unit (RRU) Remote Radio Head (RRH).

Note that although terminology from one particular wireless system, such as, for example, 3GPP LTE and/or New Radio (NR), may be used in this disclosure, this should not be seen as limiting the scope of the disclosure to only the aforementioned system. Other wireless systems, including without limitation Wide Band Code Division Multiple Access (WCDMA), Worldwide Interoperability for Microwave Access (WiMax), Ultra Mobile Broadband (UMB) and Global System for Mobile Communications (GSM), may also benefit from exploiting the ideas covered within this disclosure.

Note further, that functions described herein as being performed by a wireless device or a network node may be distributed over a plurality of wireless devices and/or network nodes. In other words, it is contemplated that the functions of the network node and wireless device described herein are not limited to performance by a single physical device and, in fact, can be distributed among several physical devices.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Some embodiments are directed to digital phase locked loop (PLL) compensation of amplitude-to-phase (AM-PM) variations in a transmitter of a radio interface of a network node or wireless device (WD). As used herein, the term “phase locked loop (PLL)” refers to a control loop having a digitally controlled oscillator (DCO) where the DCO has a frequency that is determined by a frequency control word that is based on a detected phase of the DCO with respect to a reference signal. The frequency control word is determined by a filtered output of a phase detector. Also, as used herein the term “phase variations” refers to the AM- PM variations that are to be compensated by the PLL. The term “phase modulation” refers to the phase modulation of the transmit chain input signals that are to be processed and transmitted by the transmitter. The phase variations of the transmit chain output signals are compensated for by methods disclosed herein. The term “counteracting phase modulation” is a phase modulation that is determined to counteract the phase variations according to methods disclosed herein. The term “transmit chain input signal(s)” refer to in-phase (I) signals and quadrature (Q) signals generated within a radio interface that are input to a transmit chain that includes, for example, a digital-to-analog converter, baseband processing (such as filtering), an IQ frequency up-conversion mixer and a power amplifier. The term “local oscillator (LO) signal” refers to an output of a digitally controlled oscillator (DCO). The LO signal is used in the IQ frequency up-conversion mixer to upconvert a signal to be amplified by the power amplifier.

In some embodiments, processing circuitry is added to the conventional PLL components (including a phase detector, loop filter and DCO) to compensate for AM-PM variations in the PA. These phase variations arise due to non-linear effects in the PA, where an input signal with changed amplitude but with unaltered phase, may produce a phase- shifted PA output signal. Compensation for these phase variations may be achieved with amplitude dependent phase modulation of the output of the DCO. In some embodiments disclosed herein, frequency control of the DCO output, which conventionally comes from an output of the loop filter of the PLL, may be modified according to an AM-PM compensation signal. The AM-PM compensation signal may be generated by differentiating a counteracting phase modulation. The phase modulation of the DCO may be made transparent to the PLL by subtracting the counteracting phase modulation with proper delay and magnitude from the output of the phase detector of the PLL. The counteracting phase modulation is determined to counteract phase deviations arising from the AM-PM of the PA of the radio interface. In a calibration procedure, the digital phase error signal input to the PLL loop filter is correlated with the counteracting phase modulation signal to indicate whether the PLL reacts to the counteracting phase modulation signal. Then, the magnitude of the input signal to the DCO or the counteracting phase modulation signal subtracted from the output of the phase detector may be adjusted to minimize the correlation.

For very wideband frequency channels, the non-linear DCO frequency tuning can be characterized by a stepped PLL frequency sweep, with the DCO input signal being stored in a look-up table at each step. Interpolation can then be used, followed by inversion, to create a compensation block to be used between the differentiator and the DCO to linearize the DCO frequency control response by pre-distortion.

Referring now to the drawing figures, in which like elements are referred to by like reference numerals, there is shown in FIG. 1 a schematic diagram of a communication system 10, according to an embodiment, such as a 3 GPP -type cellular network that may support standards such as LTE and/or NR (5G), which comprises an access network 12, such as a radio access network, and a core network 14. The access network 12 comprises a plurality of network nodes 16a, 16b, 16c (referred to collectively as network nodes 16), such as NBs, eNBs, gNBs or other types of wireless access points, each defining a corresponding coverage area 18a, 18b, 18c (referred to collectively as coverage areas 18). Each network node 16a, 16b, 16c is connectable to the core network 14 over a wired or wireless connection 20. A first wireless device (WD) 22a located in coverage area 18a is configured to wirelessly connect to, or be paged by, the corresponding network node 16a. A second WD 22b in coverage area 18b is wirelessly connectable to the corresponding network node 16b. While a plurality of WDs 22a, 22b (collectively referred to as wireless devices 22) are illustrated in this example, the disclosed embodiments are equally applicable to a situation where a sole WD is in the coverage area or where a sole WD is connecting to the corresponding network node 16. Note that although only two WDs 22 and three network nodes 16 are shown for convenience, the communication system may include many more WDs 22 and network nodes 16.

Also, it is contemplated that a WD 22 can be in simultaneous communication and/or configured to separately communicate with more than one network node 16 and more than one type of network node 16. For example, a WD 22 can have dual connectivity with a network node 16 that supports LTE and the same or a different network node 16 that supports NR. As an example, WD 22 can be in communication with an eNB for LTEZE-UTRAN and a gNB for NR/NG-RAN. Example implementations, in accordance with an embodiment, of the WD 22 and network node 16 discussed in the preceding paragraphs will now be described with reference to FIG. 2.

The communication system 10 includes a network node 16 provided in a communication system 10 and including hardware 28 enabling it to communicate with the WD 22. The hardware 28 may include a radio interface 30 for setting up and maintaining at least a wireless connection 32 with a WD 22 located in a coverage area 18 served by the network node 16. The radio interface 30 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and/or one or more RF transceivers. The radio interface 30 includes an array of antennas 34 to radiate and receive signal(s) carried by electromagnetic waves.

In some embodiments, the radio interface 30 includes a phase locked loop 60 having processing circuitry 62. The processing circuitry 62 may include mapper 24 configured to map an envelope of an input signal to be processed and amplified to obtain a counteracting phase modulation. The processing circuitry 62 may also include a differentiator and scaling unit 64 configured to determine an AM-PM compensation signal based at least in part on differentiation of the counteracting phase modulation. The processing circuitry 62 may include a processor, such as a central processing unit and memory. The processing circuitry 62 may comprise integrated circuitry for processing and/or control, e.g., one or more processors and/or processor cores and/or FPGAs (Field Programmable Gate Array) and/or ASICs (Application Specific Integrated Circuitry) adapted to execute instructions. The processing circuitry 62 may be configured to include memory accessible by a processor of the processing circuitry 62 (e.g., write to and/or read from). Such memory may comprise any kind of volatile and/or nonvolatile memory, e.g., cache and/or buffer memory and/or RAM (Random Access Memory) and/or ROM (Read-Only Memory) and/or optical memory and/or EPROM (Erasable Programmable Read-Only Memory).

In the embodiment shown, the hardware 28 of the network node 16 further includes processing circuitry 36. The processing circuitry 36 may include a processor 38 and a memory 40. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 36 may comprise integrated circuitry for processing and/or control, e.g., one or more processors and/or processor cores and/or FPGAs and/or ASICs adapted to execute instructions. The processor 38 may be configured to access the memory 40, which may comprise any kind of volatile and/or nonvolatile memory, e.g., cache and/or buffer memory and/or RAM and/or ROM and/or optical memory and/or EPROM.

Thus, the network node 16 further has software 42 stored internally in, for example, memory 40, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the network node 16 via an external connection. The software 42 may be executable by the processing circuitry 36. The processing circuitry 36 may be configured to control any of the methods and/or processes described herein and/or to cause such methods, and/or processes to be performed, e.g., by network node 16. Processor 38 corresponds to one or more processors 38 for performing network node 16 functions described herein. The memory 40 is configured to store data, programmatic software code and/or other information described herein. In some embodiments, the software 42 may include instructions that, when executed by the processor 38 and/or processing circuitry 36, causes the processor 38 and/or processing circuitry 36 to perform the processes described herein with respect to network node 16.

The communication system 10 further includes the WD 22 already referred to. The WD 22 may have hardware 44 that may include a radio interface 46 configured to set up and maintain a wireless connection 32 with a network node 16 serving a coverage area 18 in which the WD 22 is currently located. The radio interface 46 may be formed as or may include, for example, one or more RF transmitters, one or more RF receivers, and/or one or more RF transceivers. The radio interface 46 includes an array of antennas 48 to radiate and receive signal(s) carried by electromagnetic waves. In some embodiments the hardware 34 may also include processing circuitry 50 which may include a processor 52 and a memory 54.

In some embodiments, the radio interface 46 includes a phase locked loop 66 having processing circuitry 68. The processing circuitry 68 may include mapper 26 configured to map an envelope of an input signal to be processed and amplified to obtain a counteracting phase modulation. The processing circuitry 68 may also include a differentiator and scaling unit 70 configured to determine an AM-PM compensation signal based at least in part on differentiation of the counteracting phase modulation. The processing circuitry 68 may include a processor, such as a central processing unit and memory. The processing circuitry 68 may comprise integrated circuitry for processing and/or control, e.g., one or more processors and/or processor cores and/or FPGAs and/or ASICs adapted to execute instructions. The processing circuitry 68 may be configured to include memory accessible by a processor of the processing circuitry 68. Such memory may comprise any kind of volatile and/or nonvolatile memory, e.g., cache and/or buffer memory and/or RAM and/or ROM and/or optical memory and/or EPROM.

The hardware 44 of the WD 22 may also include processing circuitry 50. The processing circuitry 50 may include a processor 52 and memory 54. In particular, in addition to or instead of a processor, such as a central processing unit, and memory, the processing circuitry 50 may comprise integrated circuitry for processing and/or control, e.g., one or more processors and/or processor cores and/or FPGAs and/or ASICs adapted to execute instructions. The processor 52 may be configured to access (e.g., write to and/or read from) memory 54, which may comprise any kind of volatile and/or nonvolatile memory, e.g., cache and/or buffer memory and/or RAM and/or ROM and/or optical memory and/or EPROM.

Thus, the WD 22 may further comprise software 56, which is stored in, for example, memory 54 at the WD 22, or stored in external memory (e.g., database, storage array, network storage device, etc.) accessible by the WD 22. The software 56 may be executable by the processing circuitry 50. The software 56 may include a client application 58. The client application 58 may be operable to provide a service to a human or non-human user via the WD 22.

The processing circuitry 50 may be configured to control any of the methods and/or processes described herein and/or to cause such methods, and/or processes to be performed, e.g., by WD 22. The processor 52 corresponds to one or more processors 52 for performing WD 22 functions described herein. The WD 22 includes memory 54 that is configured to store data, programmatic software code and/or other information described herein. In some embodiments, the software 56 and/or the client application 58 may include instructions that, when executed by the processor 52 and/or processing circuitry 50, causes the processor 52 and/or processing circuitry 50 to perform the processes described herein with respect to WD 22.

In some embodiments, the inner workings of the network node 16 and WD 22 may be as shown in FIG. 2 and independently, the surrounding network topology may be that of FIG. 1.

The wireless connection 32 between the WD 22 and the network node 16 is in accordance with the teachings of the embodiments described throughout this disclosure. More precisely, the teachings of some of these embodiments may improve the data rate, latency, and/or power consumption and thereby provide benefits such as reduced user waiting time, relaxed restriction on file size, better responsiveness, extended battery lifetime, etc. In some embodiments, a measurement procedure may be provided for the purpose of monitoring data rate, latency and other factors on which the one or more embodiments improve.

Although FIGS. 1 and 2 show various “units” such as mapping units 24 and 26 as being within respective processing circuitry 62, 68, it is contemplated that these units may be implemented such that a portion of the unit is stored in a corresponding memory within the processing circuitry 62, 68. In other words, the units may be implemented in hardware or in a combination of hardware and software within the processing circuitry.

FIG. 3 is a simplified block diagram of a system for implementing the methods described herein and FIG. 4 is a more detailed block diagram of an example radio interface 30, 46. An envelope detector 72 determines an envelope of the transmit chain input signals that are to be processed and amplified by a power amplifier (PA) 74 (shown in FIG. 4) of the radio interface 30, 46. The transmit chain input signals include an in-phase (I) signal and a quadrature phase (Q) signal, where the I and Q signals are cartesian coordinate signals. In polar form, the amplitude and phase of the input signal are a function of the I and Q signals so that the information in the I and Q signals may be represented as follows:

Am = .jim ² + Qm ²

6(t) = arctcm(Q(t)//(t)) where Aft) is the amplitude of the input signal and 6 ft) is the phase of the input signal. (When I is less than zero, 180 degrees may be added to 6ft) to provide a range of 360 degrees.) The I and Q signals vary with time, /, and therefore so do the amplitude Aft) and phase 6ft). The relationship between cartesian and polar coordinates is nonlinear, and AM-AM and AM-PM distortion of the power amplifier output signal are related to amplitude and phase, i.e. the polar coordinates. The nonlinear relationship between cartesian and polar coordinates causes an expansion in bandwidth from the nominal bandwidth of the transmit chain input signals. For transmit chain input signals having a wide bandwidth, this bandwidth expansion combined with linearization to avoid adjacent channel interference using a digital predistorter increases difficulty of implementation of digital to analog conversion and filtering in the transmit chain of the radio interface 30, 46.

The envelope detection by the envelope detector 72 may be used because the phase distortion of the PA depends on the amplitude of the transmit chain input I and Q signals. The non-linear mapping operation 24, 26 translates the envelope signal to a counteracting phase modulation to counteract the phase deviations caused by AM-PM in the power amplifier 74 (shown in FIG. 4). This process uses knowledge about the AM-PM variations of the power amplifier 74, which may be similar to operating a digital pre-distorter (DPD). The mapping of the envelope to signal detected by the envelope detector 72 to AM-PM phase variations may be calibrated for the power amplifier 74, and/or may be based on a behavior profile of the particular power amplifier. The mapping of the mapping unit 24, 26 may be stored in a look up table (LUT) which may be stored in a memory, such as memory 40, 54, or a local memory in the radio interface 30, 46. Differentiator and scaling unit 64, 70, converts the counteracting phase modulation from the nonlinear mapping 24, 26, to a frequency modulation by differentiating the counteracting phase modulation. Scaling is then performed to scale the frequency modulation to adapt the frequency modulation to a tuning sensitivity of the digitally controlled oscillator (DCO), shown in FIG. 4.

FIG. 4 is a more detailed block diagram of the radio interface 30, 46 with the processing circuitry 62, 68 shown as part of a phase locked loop (PLL) 60, 66. The processing circuitry 62, 68 includes the envelope detector 72, the mapper 24, 26, a differentiator and scaling unit 64, 70, delay and scaling unit 75 and adders 76 and 78. A phase detector 80, loop filter 82 and a DCO 84 may be implemented by conventional phase locked loop (PLL) components. The phase detector 80 detects a phase of the local oscillator signal output by the DCO 84 with respect to the reference signal FREF. In one example, the phase detector may include a TDC 86 and a counter 88 used to detect phase. Other known phase detector configurations may be employed and implemented in place of the phase detector 80 shown in FIG. 4. The operation of the processing circuitry 62, 68 and its components are described in more detail below.

In the transmit chain of the radio interface 30, 46, the transmit chain input signal is converted to an analog signal via the transmit (TX) digital-to-analog converter (DAC) 90. The analog signal from TX DAC 90 is processed in the TX baseband (BB) path 92. The processed signal from the TX BB path 92 is mixed with the local oscillator signal from the DCO 84 by the IQ mixer 94, which upconverts the frequency of the processed signal received from the TX BB path 92 to a radio frequency (RF). The output of the IQ mixer 94 is input to the PA 74 and transmitted by the antennas 34, 48. The transmit chain of the radio interface will typically also include other components not shown such as variable gain amplifiers and radio frequency filters. Even though the local oscillator (LO) port of the IQ mixer 94 that receives the output of the DCO 84 operates in a large signal nonlinear mode, there may be a linear transfer function from the phase of the LO port signal of the IQ mixer 94 to the phase of the output signal of the IQ mixer 94. Furthermore, when performing phase shift in an oscillator, a linear phase shift can be obtained also when large phase excursions are needed, since a frequency shift can be integrated to a large phase shift over a long enough time duration. However, when the phase shift must be accomplished more quickly in some embodiments, that may correspond to a large frequency shift. Then, non-linear DCO frequency tuning characteristics can affect the operation. However, the frequency deviation requirements to counteract AM- PM nonlinearity may be limited. A DCO already exists in a digital PLL and a change of the control word will shift the frequency f from carrier frequency f ₀ to f ₀ + 6f, which after a time T will result in a phase shift 60, here in degrees. For a step change in frequency, this can be expressed as follows:

60 = 8f ■ T ■ 360 where

3f = f ~ f ₀

Thus, the differentiator and scaling unit 64, 70 may be configured to differentiate the counteracting phase modulation from the mapping unit 24, 26 to produce a frequency difference to vary the frequency control word received by the adder 78 from the loop filter 82.

The loop bandwidth of the digital PLL 60, 66 will typically be much lower than the bandwidth of the phase variations of the PA 74. The components of the PLL are configured to counteract the phase deviations inside the PLL bandwidth, which will cause the transmitter to be affected by low frequency phase variations, and it will also introduce phase settling transients with a time duration proportional to the inverse of the PLL bandwidth when switching the transmitted signal on and off (in a time division duplex (TDD) system), which may affect the performance.

To prevent the PLL 60, 66 from counteracting phase modulation of the AM-PM compensation signal and to reduce transient settling times in a TDD system, the counteracting phase modulation output from the nonlinear mapper 24, 26, can be used. The counteracting phase modulation optionally may be delayed and scaled by the delay and scaling unit 75. The optionally delayed and scaled counteracting phase modulation is subtracted in the adder 76 from the detected phase modulation output by the phase detector 80 to produce a phase error signal. The phase error signal is filtered by the loop filter 82 to produce a frequency control word. The frequency control word is added to an AM-PM compensation signal from the differentiator and scaling unit 64, 70 in the adder 78.

The output of the adder 78 is input to the DCO 84 and directly causes frequency modulation in the DCO 84. This frequency modulation corresponds to a phase modulation that is detected by the phase detector 80. In some embodiments, the phase detector 80 includes a time to digital converter (TDC) 86, which may be configured with additional dynamic range to accurately detect the additional phase deviations. When a properly delayed and scaled counteracting phase modulation signal is subtracted in adder 76 from the output of the TDC 86, the output of the adder 76 will be corrected for (i.e., will not contain any part of) the phase deviations of the PA 74 caused by AM-PM. In some digital PLLs, rather than a TDC 86, a digital to time converter (DTC) may be employed. In the DTC the time delay of the signal is set by a digital control word, and by adding a properly scaled and delayed counteracting phase modulation signal to the digital control word, the phase deviations introduced in the DCO output signal to compensate for the AM-PM of the PA 74 may be eliminated at the DTC output so that they are not detected by the phase detector 80. To suppress these phase deviations, the DTC may be configured with additional dynamic range.

Thus, in some embodiments, the processing circuitry 62, 68 is configured to determine a phase adjustment signal by at least one of delaying and scaling, via the delay and scaling unit 75, the counteracting phase modulation and then subtracting, via the adder 76, the delayed, scaled counteracting phase modulation from the phase modulation detected by the phase detector 80. In some embodiments, an amount of delay is based at least in part on at least one of a delay associated with the differentiation, and a delay associated with a response time of the DCO 84 and the TDC 86. More particularly, the delay of the path that includes the differentiator and scaling unit 64, 70, via of adder 78, DCO 84 and TDC 86 may be configured to be matched by the delay through the delay and scaling unit 75. Also, in some embodiments there may be a frequency divider in the path between the DCO 84 and the TDC 86, which introduces some delay In some embodiments, the AM-PM compensation signal is determined based at least in part on scaling the differentiated counteracting phase modulation via the differentiator and scaling unit 64, 70. In some embodiments, an amount of the scaling is predetermined to minimize the phase error signal that is output by the adder 76. In some embodiments, the processing circuitry 62, 68 is configured in a calibration mode to determine an amount of the scaling based at least in part on correlating the output signal of the adder 76 with the phase adjustment signal that is output by the delay and scaling unit 75, and adjusting the amount of scaling to drive the correlation toward zero. In some embodiments, the processing circuitry is configured in a calibration mode to determine an amount of the scaling based at least in part on: locking the PLL at each of a plurality of frequencies, and for each frequency at which the PLL is locked, storing the frequency control word. In some embodiments, the processing circuitry 62, 68 is configured to curve-fit to obtain a function describing the frequency control characteristic of the DCO 84, and using the function to determine the scaling factor to be applied by the differentiator and scaling unit 64, 70, when operating at different center frequencies and frequency deviations. Thus, having information about the frequency control characteristics of the DCO 84 may enable the frequency of the DCO 84 to be set accurately by the differentiator and scaling unit 64, 70. In some embodiments, the mapping implemented by the mapping unit 24, 26 is based at least in part on an inverse of the phase deviations arising from the non-linearity of the power amplifier. In some embodiments, the mapping is stored in a lookup table that relates envelope values to corresponding phase deviations. In some embodiments, the mapping is based at least in part on a predetermined AM-PM characteristic of the power amplifier 74. In some embodiments, the mapping is nonlinear. In some embodiments, the nonlinearity is determined by curve fitting.

In a first calibration procedure for a fractional-N digital PLL, such as the example PLL 60, 66 shown in FIG 4 using the TDC 86, the output of the TDC 86 may accurately be calibrated to the period of the carrier frequency on which the signal from the radio interface 30, 46 is transmitted to minimize fractional operation spurs that may arise due to fractional frequency operation (i.e., operating a frequency that is not an integer multiple of the reference frequency). However, the gain of the DCO 84 may be unknown. Thus, scaling after differentiation may need calibration. Such calibration may be based on the fact that when correctly calibrated, the amount of phase modulation of the signal entering the loop filter 82 will be minimized. The scaling of the delay and scaling unit 75 is set in accordance with the known TDC steps per cycle used in the calibration of the fractional PLL. Using digital correlation between the detected phase error signal input to the loop filter 82 and the output signal of the delay and scaling unit 75 will enable detection of both polarity and magnitude of phase modulation of the signal entering the loop filter. The signal scaling by the differentiator and scaling unit 64, 70 can then be altered to minimize the digital correlation to achieve calibration of the PLL 60, 66.

In a second calibration procedure to characterize the DCO 84, non-linear behavior of the frequency tuning characteristic of the DCO 84 can also be taken into account. In an example of the second calibration procedure, the PLL 60, 66 is sequentially locked to a plurality of different frequencies and for each frequency, the locked-state DCO frequency control word that is output by the loop filter 82 is recorded. The gain of the DCO 84 can then be found by curve fitting, e.g., with a polynomial. The output of the differentiation by the differentiator and scaling unit 64, 70 may be linearly or nonlinearly scaled by the differentiator and scaling unit 64, 70 based on the curve-fitted gain. This calibration process may be more time-consuming than the first calibration procedure. When the modulated signal is not so wideband that the nonlinear tuning effects are prominent, the first calibration scheme may be sufficient and may reduce calibration time.

Due to the time taken by the differentiator and scaling unit 64, 70 and DCO 84 to shift the phase of the DCO output signal, and due to delay in signal conversion by the TDC 86, a digital time delay of the counteracting phase modulation may be performed by the delay and scaling unit 75. The counteracting phase modulation and the output of the TDC 86 should preferably arrive at the adder 76 simultaneously for optimal cancellation. Note that an integer multiple of the reference frequency received by the TDC 86 may be used as a clock frequency in the processing circuitry 62,68 to support wideband signal modulation, or if the reference frequency of the PLL 60, 66 is high enough, wideband signal modulation may be possible also using the reference frequency of the PLL 60, 66 as the clock.

Since the phase modulation of the local oscillator signal from the DCO 84 will linearly translate to the output of the IQ mixer 94, no additional scaling in the PLL 60, 66 is employed, in some embodiments. However, since a digital version of the input signal to the envelope detector 72 is used by the envelope detector 72 to create the envelope signal, a constant time delay may be added to compensate for the time it takes for the signal to pass though analog baseband processing in the transmit baseband (BB) path 92. The time delay may take into account the delay of the differentiator and scaling unit 64, 70, which is typically one clock cycle of the DCO 84 update frequency, plus the delay of the DCO 84. In some embodiments, a delay may be added before or after the envelope detector 72 and/or the mapping unit 24, 26, for further delay compensation.

The bandwidth of the PLL 60, 66 may typically be much lower than the bandwidth of the phase variations. The effect of the PLL on the phase variations may therefore be limited. It should be noted, however, that the switching that occurs in a TDD system causes PLL settling transients due to an average phase difference between the TX on and TX off states when performing AM-PM mitigation. The PLL settling transients may affect the performance of the communication system. To prevent the PLL 60, 66 from counteracting the phase modulation of the AM-PM compensation signal, and to minimize settling transients in a TDD system, a phase adjustment signal may be subtracted from the detected phase modulation output of the phase detector 80. The subtraction is performed by adder 76 to produce a phase error signal. Depending on the architecture of the digital PLL 60, 66 the phase detector 80 can have different implementations. In some embodiments, the result of the phase detection by the phase detector 80 is supplied by a time to digital converter (TDC) 86. The TDC 86 may be configured to have additional range to accurately detect additional phase modulation. If a properly delayed and scaled counteracting phase modulation signal is subtracted from the output of the TDC 86 by adder 76, the signal that results from the subtraction will not contain the phase modulation of the counteracting phase modulation signal. Therefore, the PLL 60, 66 does not cancel or counteract the phase modulation of the AM-PM compensation signal, but allows the AM-PM compensation signal to modulate the DCO 84 to mitigate the transmitter output signal phase deviations caused by AM-PM in the power amplifier 74.

In some other digital PLL architectures, the DCO output signal is input to a digital to time converter (DTC) before phase detection. In the DTC, the time delay of the signal imposed by the DTC may be set by a digital control word. By adding a properly scaled and delayed phase counteraction phase modulation signal to the digital control word, the DTC may eliminate the phase modulation at its output, so that the phase modulation of the counteracting phase modulation signal is not sensed by the phase detector 80, and the PLL 60, 66 will not respond to it. To achieve this suppression of the phase modulation of counteracting phase modulation signal, the DTC should have additional range to delay the signal.

FIG. 5 is a flowchart of an example process in a radio interface 30, 46 of a network node 16 or a WD 22 for digital phase locked loop compensation for amplitude-to-phase (AM- PM) variations. One or more blocks described herein may be performed by one or more elements of the radio interface 30, 46, such as by one or more of the PLL 60, 66, processing circuitry 62, 68, including the mapping unit 24, 26 and differentiator and scaling unit 64, 70. The radio interface 30, 46 is configured to generate, via a digitally controlled oscillator (DCO) 84 of a phase-locked loop, PLL, 60, 68, a local oscillator signal based at least in part on a sum of a frequency control word and an AM-PM compensation signal (Block S10). The process includes detecting, via a phase detector 80 of the PLL 60, 66, a phase deviation of the local oscillator signal (Block S12). The process also includes filtering, via a loop filter 82 of the PLL 60, 66, a phase error signal to produce the frequency control word, the phase error signal being determined by subtracting a phase adjustment signal from the detected phase deviation, the phase adjustment signal being based at least in part on a counteracting phase modulation to counteract AM-PM variations (Block S14). The process further includes detecting, via an envelope detector 72, an envelope of a signal received by the transmit chain of the radio interface 30, 46 (Block S16). The process also includes mapping, via a mapping unit 24, 26, the envelope of the input signal to obtain the counteracting phase modulation (Block SI 8). The process further includes determining, via a differentiation and scaling unit 64, 70, the AM-PM compensation signal based at least in part on differentiation of the counteracting phase modulation (Block S20).

In some embodiments, the process includes determining the phase adjustment signal by at least one of scaling and delaying, via the delay and scaling unit 75, the counteracting phase modulation and then subtracting, via the adder 76, the phase adjustment signal from the detected phase deviation of the local oscillator signal. In some embodiments, an amount of delay is based at least in part on at least one of a delay associated with the differentiation, and a delay associated with a response time of the DCO 84 and the phase detector 80. In some embodiments, the AM-PM compensation signal is determined based at least in part on scaling, by the differentiator and scaling unit 64, 70, the differentiated counteracting phase modulation. In some embodiments, an amount of the scaling is predetermined to minimize the phase error signal. In some embodiments, the method also includes, in a calibration mode, determining an amount of the scaling based at least in part on correlating the phase error signal at the loop filter 82 input with the phase adjustment signal, and adjusting the scaling to drive the correlation toward zero. In some embodiments, the method includes, in a calibration mode, determining an amount of the scaling based at least in part on: locking the PLL 60, 66 at each of a plurality of frequencies, and for each frequency at which the PLL 60, 66 is locked, storing the frequency control word. In some embodiments, the process also includes curve-fitting to obtain a function describing the frequency control characteristic of the DCO, and using the function for the DCO frequency control characteristic when determining the scaling factor when operating at different center frequencies and frequency deviations. In some embodiments, the mapping is based at least in part on an inverse of the phase modulation arising from the non-linearity of the power amplifier. In some embodiments, the mapping is stored in a lookup table that relates envelope values to corresponding phase deviations. In some embodiments, the mapping is based at least in part on a predetermined AM-PM characteristic of the power amplifier. In some embodiments, the mapping is nonlinear. In some embodiments, the nonlinearity is determined by curve fitting. A class AB power amplifier, operating at 27 GHz, was implemented in a 22nm FD- SOI CMOS technology and simulated using a Cadence circuit simulator. The AM-PM characteristic of this power amplifier is shown in FIG. 6. A 400 MHz instantaneous bandwidth, 64-constellation point quadrature amplitude modulation (64-QAM) modulated IQ signal, with a peak to average ratio (PAR) of 7 dB, was used to generate a time domain envelope signal according to Env(t) = 7 ² + Q(t) ² as shown in FIG. 7. A third order polynomial was fitted to the AM-PM characteristic in FIG. 6, and together with the time domain envelope signal in FIG. 7, it was used to estimate the phase modulation due to AM- PM introduced by the PA. The phase distortion was then sign inverted (to find the LO signal that counteracts it), see FIG. 8. It was then differentiated with respect to time (to obtain frequency deviation), and scaled from degrees to cycles (to obtain the frequency deviation in Hz) as follows: 1 360

This is plotted in FIG. 9 which indicates that even for a rather high frequency modulation bandwidth (instantaneous bandwidth (IBW) equal to 400MHz), using a PA with relatively high AM-PM (18 degrees at signal peaks), the required frequency modulation at the output of the DCO 84 is feasible (slightly exceeding ±40MHz at the peaks, e.g., ±IBW710).

As will be appreciated by one of skill in the art, the concepts described herein may be embodied as a method, data processing system, computer program product and/or computer storage media storing an executable computer program. For example, although the processing circuitry 62, 68 may be implemented in application specific integrated circuitry, at least some of the functions performed by the processing circuitry 62, 68 may be performed by a computer processor executing software. Accordingly, the concepts described herein may take the form of an entirely hardware embodiment or an embodiment combining software and hardware aspects all generally referred to herein as a “circuit” or “module.” Any process, step, action and/or functionality described herein may be performed by, and/or associated to, a corresponding module, which may be implemented in software and/or firmware and/or hardware.

Some embodiments are described herein with reference to flowchart illustrations and/or block diagrams of methods, systems and computer program products. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions and/or application specific hardware. Computer program instructions may be provided to a processor of a general purpose computer (to thereby create a special purpose computer), special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable memory or storage medium that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instruction means which implement the function/act specified in the flowchart and/or block diagram block or blocks.

Many different embodiments have been disclosed herein, in connection with the above description and the drawings. It will be understood that it would be unduly repetitious and obfuscating to literally describe and illustrate every combination and subcombination of these embodiments. Accordingly, all embodiments can be combined in any way and/or combination, and the present specification, including the drawings, shall be construed to constitute a complete written description of all combinations and subcombinations of the embodiments described herein, and of the manner and process of making and using them, and shall support claims to any such combination or subcombination.

Abbreviations that may be used in the preceding description include:

ACLR Adjacent Channel Leakage Ratio

AM-AM Amplitude Modulation to Amplitude Modulation AM-PM Amplitude Modulation to Phase Modulation

BB Base-Band

BW Bandwidth

CMOS Complementary Metal Oxide Semiconductor

DAC Digital to Analog Converter

DCO Digitally Controlled Oscillator

DPD Digital Pre-Distortion

DTC Digital to Time Converter

Env Det Envelope Detector

EVM Error Vector Magnitude

FD-SOI Fully Depleted Silicon on Insulator I In-phase signal

IBW Instantaneous Bandwidth

LF Loop Filter

LO Local Oscillator

LUT Look-Up Table

PFD Phase Frequency Detector

PLL Phase Locked Loop

TDC Time to Digital Converter

DCO Digitally Controlled Oscillator

PA Power Amplifier

PAR Peak to Average Ratio

Q Quadrature-phase signal

RF Radio Frequency

TDC Time to Digital Converter

TX Transmitter

It will be appreciated by persons skilled in the art that the embodiments described herein are not limited to what has been particularly shown and described herein above. In addition, unless mention was made above to the contrary, it should be noted that all of the accompanying drawings are not to scale. A variety of modifications and variations are possible in light of the above teachings without departing from the scope of the following claims.