DIGITAL PHASE LOCKED LOOP AND METHOD FOR ELIMINATING GLITCH

WIPO Patent Application WO/2010/031279

A1

A digital phase locked loop and a method for eliminating glitch are provided, which belong to the electrical technical field. The digital phase locked loop includes a trigger and a delay line. The method includes: the trigger receiving a delayed time signal output from the delay line at the trigger end, and receiving a signal from the selection end of the first delay unit within the delay line at the input end, the selection end of the first delay unit being in the gating state before the trigger being triggered; the trigger sampling the signal of the selection end of the first delay unit with the delayed clock signal, and outputting the sampled signal to the selection end of the second delay unit within the delay line, the selection end of the second delay unit being in the gating state after the trigger being triggered. The embodiment of the invention samples the signal of the selection end of the first delay unit by the trigger using the delayed clock signal, uses the sampled result as the signal of the selection end of the second delay unit, thus avoids the glitch due to the transition occurred when the order of the delay is updated at the edge of the clock effectively.

JP3729041	CLOCK CORRECTION CIRCUIT
JPH11312025	CLOCK GENERATING CIRCUIT
JPH10501061	[Title of Invention] Phase Noise Detector

WAN CHEN (CN)

PCT/CN2009/072932

March 25, 2010

July 27, 2009

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HUAWEI TECH CO LTD (CN)
WAN CHEN (CN)

H03L7/00

CN1964189A	2007-05-16
CN1150354A	1997-05-21
US7388414B1	2008-06-17
US6239627B1	2001-05-29
CN101369814A	2009-02-18

BEIJING SAN GAO YONG XIN INTELLECTUAL PROPERTY AGENCY CO., LTD. (He Jing Yuan Ji Men Li, Xueyuan Road, Haidian District, Beijing 8, CN)

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