Title:
DIGITAL PHASE SYNCHRONIZING CIRCUIT, DIGITALLY-CONTROLLED OSCILLATOR, AND DIGITAL-TO-TIME CONVERTER
Document Type and Number:
WIPO Patent Application WO/2020/166645
Kind Code:
A1
Abstract:
A DTC 102, in response to an input reference clock REF, generates a first reference clock REFA. A delay circuit 122 delays the first reference clock REFA and generates a second reference clock REFB. A TDC 104 converts a phase difference between the second reference clock REFB and a feedback clock FB into a digital signal. A DCO 108 oscillates at a frequency corresponding to the output from the TDC 104 and generates an output clock OUT. A frequency divider 112A is ON/OFF switchable and, in an ON state, divides an output clock CKV by a divider ratio corresponding to a frequency control word FCW. In a first mode, the feedback clock FB is a signal obtained by re-timing the output from the frequency divider 112A by the output clock CKV. In a second mode, the feedback clock FB is a signal obtained by re-timing the first reference clock REFA by the output clock CKV.
Inventors:
OKADA KENICHI (JP)
LIU HANLI (JP)
SUN ZHENG (JP)
LIU HANLI (JP)
SUN ZHENG (JP)
Application Number:
PCT/JP2020/005456
Publication Date:
August 20, 2020
Filing Date:
February 13, 2020
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H03B5/02; H03K5/13; H03L7/08; H03L7/099; H03L7/197
Foreign References:
US20110273210A1 | 2011-11-10 | |||
JP2008054323A | 2008-03-06 | |||
JP2013042358A | 2013-02-28 | |||
JP2013058881A | 2013-03-28 |
Attorney, Agent or Firm:
ITOH Tadashige et al. (JP)
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