The present invention relates to digital-to-analogue converters and digital-to-analogue converters incorporating a filtering function and is particularly (though not exclusively) concerned with their implementation using switched-capacitor techniques.

A typical, conventional arrangement is shown in Figure 1, where successive sample values of a w-bit digital word [b b,...b....b ,] are supplied to a digital-to-analogue converter (DAC) 1 followed by an analogue FIR (finite impulse response) filter 2, based on a conventional tapped delay line structure with delays z , filter .coefficient multipliers ^h ₀ «-«h> _ι _; _ι ^{and an} adder (or of course a parallel structure may be used). The coefficients are. selected to give any desired filter response; in general this will be a baseband response from DC to half the sampling frequency F , followed by some rejection of unwanted frequencies above F /2.

The DAC may employ switched capacitor techniques (as described for example in Roubik Gregorian - "High Resolution Switched Capacitor D/A Converter" Microelectronics Journal, Vol. 12, No. 2, 1981 Mackintosh Publ. Ltd.); in the filter, the analogue delays may also be realised by switched-capacitor elements. The realisation of the analogue delays may however not be ideal.

According to one aspect of the present invention there is provided an apparatus for producing a filtered analogue output signal from a digital input signal, comprising - digital-to-analogue conversion means; delay means for producing a plurality of mutually delayed signals;

means for forming the sum of the mutually delayed signals, weighted by factors corresponding to a desired filter response; characterised in that - the delay means precedes the digital to analogue conversion means and the digital to analogue conversion means is arranged to convert each of the mutually delayed digital signals into analogue form.

In another aspect, the invention provides a switched-capacitor digital-to-analogue converter comprising inputs for receiving signals representing respective bits of a digital signal, respective switching means for supplying charge to capacitance in dependence of the states of those bits, and means for generating an analogue output signal representing the sum of these charges, charactised in that the said capacitance is a single capacitance common to all the bits and that the switching means are arranged to supply charge to the capacitor for respective different total switching times such that the charges supplied are weighted according to the significance of the bits.

Some embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:- - Figure 2 is a block diagram of one form of filtered digital-to-analogue converter according to the invention;

Figure 3 is a circuit diagram of a- known switched-capacitor unit which may be employed in the converter of Figure 1;

Figure 3a illustrates clock pulses used by the unit of Figure 3;

Figure 4 is a block diagram of a further embodiment of filtered digital-to-analogue converter;

Figure 5 is a modified version of part of Figure 3, for implementing negative filter coefficients;

Figure 6 is a circuit diagram of a digital-to-analogue converter unit according to a further 5 embodiment of the invention;

Figure 7 illustrates the clock and switching pulses employed in the unit of Figure 6; ; - Figure 8 is a block diagram of a filtered digital-to-analogue converter employing converter units of ιo the type shown in Figure 6;

Figure 9 is a modified version of part of ; Figure 6, for implementing negative filter coefficients;

* - Figure 10 illustrates a practical implementation of the converter of Figure 8; 15 - Figure 11 is a block diagram of a pulse generator for driving the converter of Figure 10; and

Figure 12 is a state diagram illustrating the operation of the generator of Figure 10.

The filtered digital-to-analogue conversion apparatus

20 shown in Figure 2 receives, as does that of Figure 1, successive w-bit digital samples of a signal to be converted. The digital words are fed to a chain of N w-bit wide D-type bistable flip-flops DO...DN-1 which are clocked at sampling rate F with clock pulses if, so

25 that a digital word, delayed by a respective number of sample periods, is available at the output of each flip-flop. These outputs are converted into analogue form by digital-to-analogue converters X0...XW-1 which produce

! at their outputs successive analogue samples corresponding

I 30 to the digital samples supplied to them. The analogue

^: . ■ outputs are multiplied by respective filter coefficients h ...h _^ ,? multipliers M0...MN-1 are shown though in practice it may be more convenient to achieve the same effect by applying appropriate reference voltages to the

converters XO etc. The weighted analogue values are then summed in an adder A.

It will be seen that the arrangement of Figure 2 performs the same conversion and filtering function of the Figure 1 arrangement, but realises the necessary delays digitally in a simple manner, at the expense however of increasing the number of digital-to-analogue converters to N (the length of the desired filter impulse response).

In principle, any suitable digital-to-analogue converters may be used for the converters XO ... XN-1, but preferably switched capacitor converters such as the (known) converter shown in Figure 3 may be employed.

In Figure 3, the input bits of a w-bit digital word are designated ^b _Q «••£>„_- _! and each serves to switch, according to its binary value, an electronic switch CS0..CSw-l (shown schematically) between zero volts (referred to below as "ground") and a reference voltage V _R . The converter contains a number of electronic switches controlled by the non-overlapping two-phase clock pulses 0 _Q , 0, at the sampling frequency F , which are shown in Figure 3a. In Figure 3 and elsewhere, the switches are shown as rectangles containing 0 or 1 indicating that the switch is closed during clock phase 0 or 1 respectively. Using the suffix i to indicate generically the components handling signals from one bit (b.) of the input bits &,-,•••&„_!' ^tlιe output of each switch CSi is connected via a switch Sli controlled by 0, to one side of a capacitor CPi, which is also connected to ground via a switch SOi controlled by 0 . The other side of each capacitor CPi is connected to a common node ND, also connected to ground by a switch SI controlled by #,. The capacitors have binary weighted values - ie the capacitance of the capacitor CPi is 2 ¹ .C where C is the value of the smallest capacitor CPO. The

node ND is also connected via a switch SO controlled by 0 to the input of a high gain inverting amplifier OA which has a negative feedback path consisting of a capacitor C„ in parallel with a switch S1F controlled by _r

During clock phase 1, the capacitor C _p is discharged via S1F. Also, each capacitor CPi is charged or discharged via switches Sli and SI to the voltage (0 or V _R ) determined by the respective switch CSi. During clock phase fi , the total charge on the capacitors CPi

w-1

0

is transferred to the capacitor C„ so that the output of the converter is W-1 ^v o = £ ^{1 • • • (ι)}

C _p i=0

Although converters of the design shown in Figure 3 could be used directly to replace the converters X0...XN-1 of Figure 2, a more practical arrangement is shown in Figure 4 where the node ND, switches SO, SI, S1F, capacitor C _p and amplifier OA are common to the N converters. The flip-flops .are as in Figure 2, whilst the capacitor/switch array units CSA0...CSAN-1 correspond to the components enclosed in the broken line box in Figure 3. In this embodiment, the capacitor values in each array are chosen to weight the contribution of that array to the final output by a factor corresponding to the

appropriate one of the desired filter coefficients

To accommodate negative coefficients, the array is modified by the transposition of the clock phases illustrated in Figure 5 by transposition of switches SOi and Sli. The nth array (n=0, ,N-1) has capacitors with values ^2l - ^c _n where C = |h j .C* (C* being a constant), so that the contribution of this array to the total output voltage is

w-1

^V o,n^ ⁼ V Σ- ^b i,n' ²ⁱ > ^• * ^"* - ⁽²⁾ C„ i=0

where z is the z-transform variable and b, „ is the ι,n value of the ith bit of the digital word at the output of the nth D-type flip-flop. The contribution of all N words for an FIR filter of length N is

N-l

N-l w-1 ^b i,n. ²ⁱ '- ^2"nl

If we set C„=2 ^W .C* then the output voltage is

If the smallest capacitance value C is C, and the corresponding value of h _n is h ^ then the remaining capacitor values are given by

and C = ,w

mm

Since C„ is usually the largest capacitor in the circuit, we obtain a maximum capacitance spread of

,

n mm • n mm l

and a total capacitor area of N-l total = ^_ [2" 2» - l.. ^ | __ _n |] i nl Imri-n n=0

- For an example of FIR filtering function with equal coefficients and unity DC gain (h =1/N, n=0, ..., N-l) the above results lead to a capacitance spread of C , = N.2 ^W and a total capacitor area of ^c tot l ^{as M} ^ ² * ^,"1 - ¹⁾ - ^c -

The embodiment of Figure 4 requires (N.w+l) capacitors and (2N.W+3) switches, increasing with both the bit resolution w of the conversion and the length N of the desired filter impulse response. This means that, even for a medium bit resolution and short filter responses, the resulting silicon area required for an integrated

circuit implementation can become rather large. An alternative converter is however now proposed, having reduced number of capacitors and switches.

Figure 6 shows a switched capacitor digital-to-analogue converter (without filtering). It can be employed alone, or, as will be described in more detail below, can be used to replace the converters X0..XN-1 of Figure 2, in the same manner as was the converter of Figure 3. Input bits b. and switches CSi perform the same functions as in Figure 3, as do switches SI, SO, SF, capacitor C„ and amplifier OA. However, the capacitors CPi and switches SO. are replaced by a single capacitor CP and switch SOA. The binary weighting of contribution of the w input bits is instead determined by the waveforms applied to the switches Sli (now designated

SAO SAi...SAw-l). Effectively the capacitor CP , is multiplexed between the input bits. A set of switching waveforms 0* , ^~ and """ ^s illustrated in Figure 7. w-1 Note that there are now 2 clock pulses

^(or p ) in one conversion period. The waveforms

A ....A , contain 1, 2, 4 etc pulses synchronous with - ie in general the waveform A- contains 2 ¹ pulses. At the beginning of each conversion period, the feedback capacitor C _p is reset by the switch SF controlled by pulse A . Pulse A also closes switch A and the capacitor CP assumes a voltage of 0 or V _R according to the state of bit b . On the following clock pulse this charge is transferred to C„. This process is repeated by pulse A, for bit b,; however, this occurs twice, as A, contains two pulses, and so forth, the D/A conversion being performed sequentially from bit b to bit b ,. The converted

output is available during pulse following the last pulse of prior to resetting of C _p by a further pulse A . Of course it is not actually necessary that the bits be processed in any particular sequence, or indeed that all the pulses for one particular bit be generated before those of another bit (though obviously the pulses must not coincide).

The equivalent bit voltage V. corresponding to each bit of the digital word is determined by the number of pulses of the corresponding switching waveform A. and can thus be expressed by

^v i ^■ W ²

and therefore the converted output is

w-1

Assuming [V _Q max /V _R .(l-2~ )] = 1, we can easily see from the above expression that the capacitance spread of the converter in Figure 6 is equal to the capacitance spread of the conventional converter of Figure 3, ie (C„/C)=2 . However, the total capacitor area is now w w+1 only (2 +1).C, compared to 2 .C in a conventional converter, and the total number of capacitors has also been reduced from (w+1) to only 2. An additional significant advantage of this new architecture is that, unlike conventional converters, the accuracy of the capacitance ratio C _p /C does not affect the required bit resolution, which depends solely on the number of time

slots of each switching waveform. Thus, we can easily apply to the converter of Figure 6 a number of well known design techniques than can significantly reduce the capacitance spread in a switched-capacitor network (eg capacitive-T network), even though this also brings an inherent reduction of the resulting accuracy of the capacitance ratios. This makes it practical to implement high resolution converters using simple switched capacitor networks occupying a small area of silicon. it is observed that, for a given maximum switching frequency, the conversion rate (and hence sampling rate of the digital words that can be accommodated) is reduced by a -factor of (2 ^W -1) relative to Figure 3; however the reduction in capacitor area and required capacitance ratio accuracy make this embodiment particularly useful for high resolution conversions at lower frequency.

An implementation of a combined digital-to-analogue converter and FIR filter based on the binary-weighted time slot array architecture described above is illustrated in Figure 8. The flip-flops Dn are shown as for Figures 2 and 4. The converters Xn of Figure 2 are replaced by time slot arrays TAO to TAN-1, followed by common components SI, SO, OA-, C„ and SF which are identical to those shown in Figure 7. Each time slot array TAi is either in the form indicated in the dotted rectangle in Figure 7 (for positive h ) or, for negative is structurally the same but is supplied with different pulses. Thus switches

SAn supplied by pulses A and switch SOA supplied with

,ι ⁿ pulses ψ are replaced by switches SBn and S1A ^~ supplied with pulses B and , , as shown in Figure

9. Pulses B (n=0...n-l) take the same form as pulses

A but are synchronous with 0 instead of 0-. .

As in the case of the architecture of Figure 2, we can easily see that the normalised output voltage conversion

level corresponding to all N digital words is also expressed by

N-l W-1

where C = |h « w

in order to preserve the gain constant of the FIR transfer function. After normalisation, we obtain

n •C

n min

\ mm

yielding a maximum capacitance spread of

_{c =} CF _{/C = 2} w ^spread '^ ^Δ

\ mm

and

N-l

n mm n = 0

for the total capacitor area. For many practical situations where the FIR filter is designed such that

N-l

n = 0

the above expression for C. , , shows a reduction of about 50% over the total capacitor area obtained with the previous realisation. Two additional advantages of the architecture with binary-weighted time slot arrays are obtained firstly with respect to the total number of capacitors, which has been ^' reduced from (N.w+1) to only (N+l), and, secondly, with respect to the required capacitance ratio accuracy of the impulse response coefficients of the FIR filter.

Figures 10 and 11 illustrage a simple practical implementation of the type of combined digital-to-analogue converter described above with reference to figure 8. It has 4-bit resolution and four equal FIR filter coefficients. The filter impulse response (in z-transform notation) is

H (z) = 1 (1 + z ^λ + z ^"2 + z ^"3 ).

There are four 4-bit wide D-type flip-flops DO, Dl, D2, D3. Note that the first of these is (as in the other

figures) not strictly necessary but is included to ensure accurate timing. Also the switches CSi are omitted (on the basis that, for a 4-bit implementation, the voltages output directly from the flip-flops are themselves sufficiently consistent). There are three stages TANO ... TAN3, of the type shown in figure 6, with equal capacitor CO ... C3 (= capacitance c) representing the four equal coefficients. Components SO, SI, SF, CF and OA are as shown in figure 6, whilst two simple sample and

10 hold circuits SHI, CHI, 0A1, SH2, CH2, 0A2 are included to sample the output (A _Q being applied to switches SHI, SH2) when conversion is completed, to eliminate any output transients during conversion. C _p is equal to 64C for

Vomax/V _R (1 - 2 ^"N ) = 1. I 15 The switching waveforms A _Q , A,, A~, A- are generated by means of the generator shown in figure 11. A square-wave oscillator OSC drives a non-overlapping phasing generator consisting of an invertor II, cross-coupled NAND gates Nl, N2, and inverters 12, 13 to ₂ 0 produce pulses JS O , 1, . A , modulo 8 binary down-counter Zl is clocked by 0. . The *1111' state is designated as an idle-state in which the counter is

^! locked by an and-gate AND1 which decodes this state to an end of conversion pulse EOC and inhibits clock pulses via

₂₅ s switch SWI in the oscillation circuit.

The generation of the required (2 ^W -1) = 15 pulses of the switching waveforms A _Q ... A ₃ is indicated by an external pulse SOC (synchronous with the digital input t ! data to be converted) which is applied to a paralled load

1 ₃₀ input PE of the counter Zl to load count '1110' into the

^■ . counter.

,1

The counter is then decremented by pulses jø, through its states to 000, during which period the counter states are decoded by inverters 14 ... 17 and and-gates

AND1 ... AND4 to produce the pulses A _Q ... A., as illustrated in the sequence diagram in figure 12. The sixteenth pulse . returns the counter to the '1111' state where it remains locked until a further start pulse SOC is received.

Note that in this converter, pulses B. are not required (since the filter coefficients are all positive) but could of cause be generated by a second counter and decoding logic similar to the arrangements for A^. A discrete component version of this converter can be constructed using amplifiers type LF353, CMOS analogue switches type CD4016, and standard CMOS logic circuits, although in practice an integrated circuit implementation is to be preferred. Typical capacitor values are C = 40pF and Cp = 2700pF (with + 0.2% of the nominal values) may be used.