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Title:
DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2021/171422
Kind Code:
A1
Abstract:
In a thin film transistor layer in which a lower wiring (18d), a flattening film (19a), an interlayer insulation film (20a), and an upper wiring (21b) are layered in order, a first contact hole (Ha) and a second contact hole (Hb) for electrically connecting the lower wiring (18d) and the upper wiring (21b) are formed in the flattening film (19a) and the interlayer insulation film (20a), respectively, and at least part of the edge part of the flattening film (19a) where the first contact hole (Ha) is formed is exposed from the edge part of the interlayer insulation film (20a) where the second contact hole (Hb) is formed.

Inventors:
INOUE SATOSHI
NISHIKI HIROHIKO
NAKANISHI TERUYUKI
Application Number:
PCT/JP2020/007765
Publication Date:
September 02, 2021
Filing Date:
February 26, 2020
Export Citation:
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Assignee:
SHARP KK (JP)
International Classes:
G09F9/00; G09F9/30; H01L27/32; H01L51/50; H05B33/02; H05B33/04; H05B33/10
Domestic Patent References:
WO2012086513A12012-06-28
WO2013108326A12013-07-25
Foreign References:
JP2014003208A2014-01-09
JP2004333642A2004-11-25
JP2019117892A2019-07-18
JP2016219362A2016-12-22
JP2019102446A2019-06-24
JP2019204967A2019-11-28
JP6648349B12020-02-14
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Download PDF:
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