CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Non-Provisional Application No. 17/337,335, entitled, “Distribution Amplifier for a Communication Device” and filed on June 2, 2021, which is incorporated herein by reference.

BACKGROUND

[0002] The present application generally relates to a distribution amplifier for a communication device.

[0003] A communication device can be used to facilitate communication between different components of a communication network. The communication device may be required to provide multiple outputs from a single input. One type of communication device, such as a gateway, may incorporate a multi-channel radio. A multi-channel radio can be made by applying an antenna signal (e.g., the input) to a number of radios (e.g., the outputs).

[0004] One way to implement a multi-channel radio is to use a combination of amplifiers and splitters that increases the signal levels (from the antenna) prior to splitting the signals for distribution of the signals to a number of radios (or receivers). The splitter can be either a resistive splitter or a multiplicity of Wilkinson splitters. The resistive splitter may not provide much isolation between the outputs of the splitter and the failure of one radio could impact other nearby radios. The Wilkinson splitters may provide some isolation between the outputs but can use a large amount of space on a circuit board and/or may result in a more expensive design. The amplifiers are typically configured to have a gain that is adequate to offset the loss of the passive splitters that follow the amplifiers. The configuration having the amplifier before the splitter makes the connected radios more susceptible to overload from the resultant gain needed in the amplifiers. In addition, even if the radios are not overloaded, the amplifiers can introduce more distortion into the signal as a result of the removal of local feedback to achieve a higher gain, which can make the amplifiers more susceptible to intermodulation distortion issues. An alternate configuration where the amplifiers follow the splitter(s) avoids the issue of overloading the radios, but can introduce noise into the signal, which is not desirable.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a block diagram showing an embodiment of a communication system.

[0006] FIG. 2 is a block diagram showing an embodiment of a gateway from the telecommunication system of FIG. 1.

[0007] FIG. 3 is a block diagram showing an embodiment of a distribution amplifier from the gateway of FIG. 2.

[0008] FIG. 4 is a circuit diagram showing an embodiment of the distribution amplifier from the gateway of FIG. 2.

[0009] FIG. 5A is a circuit diagram showing an embodiment of an approximation for a portion of the transmission line without the connection for the amplifier stage.

[0010] FIG. 5B is a circuit diagram showing an embodiment of an approximation for a portion of the transmission line with the connection for the amplifier stage.

[0011] FIG. 6 is a flowchart showing an embodiment of a process for determining the impedance of a portion of the transmission line.

[0012] FIG. 7 is a flowchart showing an embodiment of a process for simulating a microstrip design of a portion of the transmission line.

[0013] Wherever possible, the same reference numbers are used throughout the drawings to refer to the same or like parts. DETAILED DESCRIPTION

[0014] The present application generally pertains to a distribution amplifier for a communication device such as a gateway. The distribution amplifier can receive an input signal and provide multiple output signals, each having good signal integrity, to multiple radios (or receivers). The distribution amplifier can have a transmission line that receives an input signal, such as a signal from an antenna of the communication gateway. Multiple amplifier stages can be connected to the transmission line to receive the input signal. Each of the amplifier stages can be a low gain (e.g., gain ^« 1) amplifier stage and can be connected to a corresponding radio of the communication gateway.

[0015] The transmission line can be divided into multiple portions (sometimes referred to as transmission line segments) corresponding to the connection points for each of the amplifier stages. In an embodiment, the amplifier stages can be equally spaced such that the length of each portion of the transmission line (or transmission line segment) between connection points for the amplifier stages can be substantially equal (/.e., the length of each portion can be within a preselected tolerance of about 10%). In addition, the amplifier stages can be designed for low reverse transmission to maximize or otherwise increase the isolation of the outputs from the amplifier stages. An approximation of the transmission line can include the input capacitance of the amplifier stages and the inductance and capacitance of the transmission line. To obtain good fidelity versions of the input signal at each of the inputs to the amplifier stages, the unloaded impedance of the transmission line (/.e., the impedance without the input capacitance of the amplifier stages) is made higher than the desired final impedance such that the transmission line has the desired final impedance with the connections to the amplifier stages. To provide good performance, the transmission line can be driven and terminated by the desired final impedance.

[0016] FIG. 1 shows an embodiment of a communication system 10. As shown by FIG. 1, the system 10 includes a gateway 15 that can facilitate communications between a server 12 and client devices 18 such that client devices 18 can be connected to the Internet. In addition, gateway 15 can also facilitate communications between the client devices 18. The server 12 can be connected to the gateway 15 by a network (not shown in FIG. 1), such as a local area network (LAN), wide area network (WAN) or the Internet. In an embodiment, the gateway 15 can be wirelessly connected to the server 12, but may be connected to the server 12 with a wired connection in other embodiments. The gateway 15 can be connected to the client devices 18 by a network 16 (e.g., a LAN or WAN). For simplicity of illustration, FIG. 1 depicts three client devices 18 and one gateway 15 connected to network 16, but there can be any number of client devices 18 (e.g., 8 or 64 client devices associated with a gateway) or gateways 15 in other embodiments.

[0017] In one embodiment, the network 16 can be a LoRaWAN (Long Range Wide Area Network) and can be used to implement an loT (Internet of Things) ecosystem that includes the gateway 15 and the client devices 18. LoRaWAN is a long range, low power, wide area networking (LPWAN) protocol based on LoRa (Long Range) technology and can be used to wirelessly connect battery operated devices (e.g., client devices 18) to the Internet In one embodiment, LoRa technology can be a spread spectrum modulation technique derived from chirp spread spectrum (CSS) technology. The client devices 18 can include any suitable type of device or sensor used for applications such as asset tracking, equipment monitoring, lighting controls, room occupancies, biometrics/card readers, motion sensing, contact tracing, etc.

[0018] FIG. 2 shows an embodiment of the gateway 15. The gateway 15 can include an antenna 22 for receiving wireless signals. The signal received from antenna 22 can be provided to a distribution amplifier 25. The distribution amplifier 25 can provide the signal received from the antenna 22 to multiple radios 28. The radios 28 can include one or more transceivers, receivers or transmitters to send and receive signals. In one embodiment, the distribution amplifier 25 can be connected to eight (8) radios, but may be connected to more or less radios in other embodiments. In addition, it is to be understood that the gateway 15 may include additional components (e.g., power connections, network connections, processors, memory devices, etc.), which have been omitted from FIG. 2 for simplicity.

[0019] FIGS. 3 and 4 show an embodiment of the distribution amplifier 25. The distribution amplifier 25 includes a transmission line 35 that receives the signal from the antenna 22 (or other input signal) as an input (shown by the IN connection in FIG. 4). Multiple amplifier stages 38 can be connected to the transmission line 35. In one embodiment, each of the amplifier stages 38 can be independent of the other amplifier stages 38. The number of amplifier stages 38 in the distribution amplifier 25 can correspond to the number of radios 28 to be connected to the distribution amplifier 25. In an embodiment, the distribution amplifier 25 can include eight (8) amplifier stages 38 to permit eight (8) radios 28 to be connected to the distribution amplifier 25.

[0020] As shown in FIG. 4, each amplifier stage 38 can include a transistor (T1-TN) connected between the transmission line 35 and an output connection (OUT 1-OUTN). In one embodiment, the transistor (T1-TN) can be a Silicon Germanium (SiGe) bipolar junction transistor (BJT), but other types of transistors may be used in other embodiments. In each amplifier stage 38, the output connection (OUT1-OUTN) can be connected to the collector of the transistor (T1-TN) via an output capacitor (CO). In one embodiment, the output capacitor (CO) can have a capacitance of 1 nf, but may have other capacitances in other embodiments.

[0021] The collector of the transistor (T 1 -TN) can also be connected to a power source (Vcc) via a collector resistor (RC). In one embodiment, the power source (Vcc) can provide 3.3 V and the collector resistor (RC) can be 50 W. However, in other embodiments, the power source (Vcc) can provide more or less than 3.3 V and the resistance of the collector resistor (RC) can be greater or less than 50 W. The emitter of the transistor (T1-TN) can be connected to ground via an emitter resistor (RE). In one embodiment, the resistance of the emitter resistor (RE) can be 22 W, but the resistance can be greater or less than 22 W in other embodiments. The base of the transistor (T1-TN) can be connected to the transmission line 35 and can operate as the input to the amplifier stage 38.

[0022] In one of the amplifier stages 38, the DC voltage on the emitter resistor (RE) can be monitored to set the quiescent current (or DC bias) for all the amplifier stages 38 such that the transistors (T1-TN) operate in a linear fashion. Since each of the amplifier stages 38 has a similar design, only one of the amplifier stages 38 has to be monitored and the performance of the other amplifier stages 38 will be similar to the monitored amplifier stage when the operating temperature of all the amplifier stages 38 is substantially similar (e.g., within a few degrees Celsius).

[0023] In FIG. 4, a monitoring circuit 40 can be connected to the emitter resistor (RE) in the first amplifier stage 38 (/.e., the amplifier stage with transistor (T1)). The monitoring circuit 40 can be used to set the DC bias of the transistors (T 1-TN) and to drive the base of each of the transistors (T1-TN) such that the voltage at the emitter resistor (RE) matches a reference voltage. By setting the voltage at the emitter resistor (RE), the operating current of the transistor (T1-TN) can be set, which in turn, sets the collector current and sets the voltage drop across the collector resistor (RC) thereby providing for linear operation of the transistor (T1-TN).

[0024] The monitoring circuit 40 can include an op-amp (operational amplifier) 42. The op- amp 42 can receive a reference voltage (Vref) at the non-inverting input to the op-amp 42 and can receive the voltage at the emitter resistor (RE) of the first amplifier stage 38 at the inverting input to the op-amp 42. The output of the op-amp 42 can be connected to the transmission line 35 via an output resistor (RO). In addition, the output of the op-amp 42 can be connected to the inverting input of the op-amp 42 via a feedback capacitor (CFB). In one embodiment, the feedback capacitor can have a capacitance 0.01 pf and the output resistor can be 4.99 kQ. However, in other embodiments, the feedback capacitor can have a capacitance more or less than 0.01 pf and the resistance of the output resistor can be greater or less than 4.99 kQ.

[0025] Since the output of the op-amp 42 is connected to the transmission line 35, the DC voltage provided at the output of the op-amp is then provided to the bases of the transistors (T1-TN) for each of the amplifier stages 38 to control the voltage at the emitter resistor (RE) to the desired voltage (/.e., the reference voltage (Vref)). A pair of blocking capacitors (CB) can be placed at each end of the transmission line 35 to make sure that the DC voltage provided by the op-amp 42 is received by the transistors (T1-TN).

[0026] The transmission line 35 can be used to drive the amplifier stages 38 with the input signal received at the input connection (IN). The transmission line 35 can be divided into multiple portions (also referred to as transmission line segments) 35S having substantially equal lengths such that there is a portion or transmission line segment 35S for each amplifier stage 38. Each portion or transmission line segment 35S can also include a connection (or tap) 44 for an amplifier stage 38 at one end the portion or transmission line segment 35S. For example, the portion or transmission line segment 35S shown in FIG. 4 has a connection 44 for the second amplifier stage 38. Since each of the portions or transmission line segments 35S have substantially equal lengths, the corresponding connection points for the amplifier stages 38 connected to the portions or transmission line segments 35S are also substantially equally spaced apart.

[0027] The transmission line 35 can be arranged to provide good signal integrity and good high frequency characteristics to the inputs of each the amplifier stages 38 (/.e., connections 44). The transmission line 35 can be arranged such that the impedance (Zo) of the transmission line 35 (with the connections for the amplifier stages 38) matches (or is substantially equal to) both the input impedance seen at the input connection (IN) and the terminating (or load) impedance provided by resistor (RT). By having the terminating impedance be equal to the input impedance, reflections along the transmission line 35 can be avoided to provide good signal integrity. In one embodiment, the input impedance at the input connection (IN) can be 50 W, thus, the corresponding impedance (Zo) of the transmission line 35 (with the connections for the amplifier stages 38) and the resistor (RT) have to be 50 W.

[0028] FIG. 5A shows an embodiment of an approximation for a portion of the transmission line without the connection for the amplifier stage. The portion or transmission line segment 35S can be approximated by a series inductor (LS) and a shunt capacitor (CS). The capacitance approximation (CS) for the transmission line segment 35S corresponds to the capacitance per unit length (Cpu) of the transmission line segment 35S multiplied by the length (d) of the transmission line segment 35S (/.e., the distance between two connection points 44). The inductance approximation (LS) for the transmission line segment 35S corresponds to the inductance per unit length (Lpu) of the transmission line segment 35S multiplied by the length (d) of the transmission line segment 35. The capacitance approximation (CS) and the inductance approximation (LS) can then be used to determine the impedance (Zs), delay (Tds) and cutoff frequency (CFs) of the transmission line segment 35S as shown in Equations (1)-(3)

Td _s = L/LS * CS (2) where LS = Lpu * d and CS = Cpu * d.

[0029] FIG. 5B shows an embodiment of an approximation for a portion of the transmission line with the connection for the amplifier stage. Similar to the configuration in FIG. 5A, the portion or transmission line segment 35S can be approximated by the series inductor (LS) and the shunt capacitor (CS) as described above. In addition, the transmission line segment 35S can also be approximated with an amplifier capacitance (CA) corresponding to the input capacitance of the amplifier stage 38. The capacitance approximation (CS), the inductance approximation (LS) and the amplifier capacitance (CA) can then be used to determine the desired impedance (Zo), delay (Tdo) and cutoff frequency (CFo) of the transmission line segment 35S with the connection for the amplifier stage 38 as shown in Equations (4)-(6) where LS = Lpu * d and CS = Cpu * d.

[0030] To obtain the desired impedance (Zo) of the transmission line 35 (with the connections for the amplifier stage 38), the impedance (Zs) of the transmission line 35 (without the connections for the amplifier stages 38) has to be made larger than the desired impedance (Zo) to account for a reduction in impedance provided by the connection to the amplifier stage 38 (i.e., the amplifier capacitance (CA)). When arranging the distribution amplifier 25, the desired impedance (Zo) of the transmission line 35 (with the connections for the amplifier stage 38) and the terminating impedance (e.g., resistor (RT)) are known based on the input impedance seen by the distribution amplifier 25 (e.g., the input impedance of the antenna 22). Thus, the impedance (Zs) of the transmission line 35 (without the connections for the amplifier stages 38) has to be determined and implemented in the distribution amplifier to obtain the desired impedance (Zo).

[0031] FIG.6 shows an embodiment of a process for determining the impedance (Zs) of the transmission line 35 (without the connections for the amplifier stages 38). The process begins by selecting or determining the desired impedance (Zo) of the transmission line 35 (with the connections for the amplifier stages 38) (step 602). As described above, the desired impedance (Zo) is based on the input impedance to the transmission line 35. A simulation of the microstrip design for a portion or transmission line segment 35S of the transmission line 35 is performed (step 604) to determine parameters about the transmission line 35.

[0032] FIG. 7 shows an embodiment of a process for simulating a microstrip design of the portion or transmission line segment 35S of the transmission line 35 from step 604 of FIG. 6. It is to be understood that other processes for simulating the microstrip design from step 604 of FIG. 6 may be used in other embodiments. The process begins by describing and simulating the geometry for the microstrip design of the portion or transmission line segment 35S of the transmission line 35 that has the desired impedance (Zo) (step 702). The description of the geometry for the microstrip design for the transmission line segment 35S can include parameters such as the width of the trace, the location of the ground plane and the location and thickness of the dielectric material used. For example, the ground plane can be located at the bottom of the design, with 50 millimeters of dielectric material above the ground plane and a 22.5 millimeter wide trace on the dielectric material. Other geometries for the microstrip design of the transmission line segment 35S may be used in other embodiments.

[0033] During the simulation of the microstrip design, a measurement of the delay (Td _Sim ) over a predetermined distance (e.g., 1 inch) of the microstrip design located between terminations having the desired impedance (Zo) is performed (step 704). The effective relative dielectric constant (£r(eff)) is then calculated (step 706) using Equation (7) where c is the speed of light in a vacuum.

[0034] The inductance per unit length (Lpu) and the capacitance per unit length (Cpu) for the microstrip design of the transmission line segment 35S are then calculated (step 706) using Equations (8) and (9)

CVU ₌ I^irn ₌ few (9) where c is the speed of light in a vacuum.

[0035] Referring back to FIG. 6, the length (d) of the transmission line segments 35S to be implemented is determined (step 606). The length (d) of the transmission line segments 35S is selected to obtain equal spacing for the connections to the amplifier stages 38 (and equal spacing of the amplifier stages 38). The inductance (LS) for the transmission line segment 35S can then be defined using Equation (10).

LS = d * Td _sim * Z _s (10)

[0036] Next, the total capacitance (Co) that is needed for the transmission line segment 35S to have the desired impedance (Zo) is defined (step 610). The impedance (LS) can be used to define the total capacitance (Co) using Equation (11).

[0037] After the total capacitance (Co) for the for the transmission line segment 35S is defined, the impedance (ZS) for the transmission line segment 35S is determined (step 612). The capacitance (CS) for the transmission line segment 35S is defined using Equation (12).

CS = ^ (12)

[0038] Then, the capacitance (CA) of the amplifier stage is defined as the difference between the total capacitance (Co) from Equation (11) and the capacitance (CS) for the transmission line segment 35S from Equation (12) as set forth in Equation (13).

[0039] The definition of the inductance (LS) for the transmission line segment 35S from Equation (10) can be inserted into Equation (13) to obtain Equation (14).

[0040] Equation (14) can then be solved for the impedance (Zs) of the transmission line segment

35S, which is a quadratic equation that can be solved using Equations (15).

[0041] The values for the impedance (Zs) of the transmission line segment 35S can be calculated using the known or selected values for the desired impedance (Zo), the distance (d), the time delay from the simulation of the microstrip design (Td _Sim ) and the input capacitance of the amplifier stage 38 (CA). The positive root from Equations (15) can then be used for the impedance (Zs) of the transmission line segment 35S. The distribution amplifier can then be configured with transmission line segments 35S having the impedance Zs (step 614) such that when the amplifier stages 38 are connected to the transmission line 35, the transmission line 35 has the desired impedance Zo.

[0042] Although the figures herein may show a specific order of method steps, the order of the steps may differ from what is depicted. Also, two or more steps may be performed concurrently or with partial concurrence. Variations in step performance can depend on the software and hardware systems chosen and on designer choice. All such variations are within the scope of the application. Software implementations could be accomplished with standard programming techniques, with rule based logic and other logic to accomplish the various connection steps, processing steps, comparison steps and decision steps.

[0043] It should be understood that the identified embodiments are offered by way of example only. Other substitutions, modifications, changes and omissions may be made in the design, operating conditions and arrangement of the embodiments without departing from the scope of the present application. Accordingly, the present application is not limited to a particular embodiment, but extends to various modifications that nevertheless fall within the scope of the application. It should also be understood that the phraseology and terminology employed herein is for the purpose of description only and should not be regarded as limiting.