Title:
DIVISOR CONTROL CIRCUIT, FRACTIONAL FREQUENCY DIVISION DEVICE, FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIS METHOD
Document Type and Number:
WIPO Patent Application WO/2015/135490
Kind Code:
A1
Abstract:
A divisor control circuit allows a frequency divider to have a fractional divisor. The divisor control circuit includes: a multiplexer, arranged to select one of a first clock signal and a second clock signal as a multiplexed signal according to a selection signal, and accordingly provide the multiplexed signal to the frequency divider, wherein there is a phase difference between the first clock signal and the second clock signal; and a selection signal generation circuit, coupled to the multiplexer, arranged to generate the selection signal according to a frequency-divided signal outputted by the frequency divider. The multiplexer alternately selects the first clock signal and the second clock signal as the multiplexed signal during a period of the frequency-divided signal.
More Like This:
| JPS62144433 | DATA CLOCK RECOVERY CIRCUIT |
| JPH05259904 | FREQUENCY SYNTHESIZER |
Inventors:
WU MIN-JIE (SG)
Application Number:
PCT/CN2015/074123
Publication Date:
September 17, 2015
Filing Date:
March 12, 2015
Export Citation:
Assignee:
MEDIATEK SINGAPORE PTE LTD (SG)
WU MIN-JIE (SG)
WU MIN-JIE (SG)
International Classes:
H03L7/06
Foreign References:
| US20030058979A1 | 2003-03-27 | |||
| CN1996762A | 2007-07-11 | |||
| CN1565081A | 2005-01-12 | |||
| US20090168947A1 | 2009-07-02 |
Other References:
See also references of EP 3033833A4
Attorney, Agent or Firm:
BEIJING SANYOU INTELLECTUAL PROPERTY AGENCY LTD. (CN)
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