CROSS-REFERENCE TO RELATED APPLICATION

This application is related in subject matter to th copending U . S . patent application Serial No . 07/505 , 384 o David B . Ribner entitled "Third Order Sigma Delta Oversample Analog-to-Digital Converter Network with Low Componen Sens it ivity" filed April 6 , 1990 , and as s igned to th assignee of this application . The subject matter thereof i hereby incorporated by reference .

BACKGROUND OF THE INVENTION

Field of the Invention

This invention relates to oversampled analog-to-digita converters and, more particularly, to a technique fo doubling the effective operating rate of an oversample modulator to realize an increase in performance either in th form of an increase in resolution or an increase i convers ion rate , without any reduction in resolution o oversampled analog-to-digital converters . The principles o the invention are generally applicable to any oversample network, including second- and third-order oversample modulators .

General Description of the Prior Art

High resolution analog-to-digital signal conversion ca be achieved with lower resolution components through the us of an oversampled interpolative (or sigma delta) modulato followed by a digital low pass decimat ion f i lt er

Oversampling constitutes operation of the modulator at a rate many times above the signal Nyquist rate, whereas decimation constitutes reduction of the clock rate down to the Nyquist rate . Sigma delta modulators (sometimes referred to as delta sigma modulators) have been used in analog-to-digital (A/D) converters for some time. Detailed general information can be obtained from the following technical articles which are hereby incorporated by reference. 1) "A Use of Limit Cycle Oscillators to Obtain Robust Analog to Digital Converters", J.C. Candy, IE Transact-inns on Commun ^* i oati on . Vol. COM-22, No. 3, pp. 298-305, March 1974

2) "Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator", J.C. Candy et al., Transactions o_n CQIMHUniflatJPIIS, Vol. COM-24,

No. 11, pp. 1268-1275, November 1976

3) "A Use of Double Integration in Sigma Delta Modulator", J.C. Candy, TF.F.F Transactions on Commπnication. Vol. COM-33, No. 3, pp. 249-258, March 1985

Oversampled analog-to-digital converters perform a coarse quantization of their input signal at a sampling rate that is much higher than the Nyquist rate . Us ing a combination of feedback and integration, the resultin quantization noise is forced to high frequency so that its removal can be effected by low pass filtering and decimation . Enhanced resolution is obtained after these operations , bu only at the expense of a reduction in throughput from th initial conversion rate . This type of converter offers th flexibility of allowing a tradeoff between resolution in tim and resolution in amplitude . As an example, it is possibl to achieve 16-bit conversions starting with only a 1-bi quantizer .

The ratio of the initial to final conversion rates referred to as the oversampling ratio, governs the increas

in resolution that is obtained for a given design oversampled analog-to-digital converter (ADC) . For a secon order modulator design, for instance, resolution improves 2.5 bits for each doubling of the oversampling ratio, a increases to 3.5 bits for a third-order modulator. It wou be desirable to operate with as high an oversampling ratio possible; however, for a specified final conversion rat circuit speed will impose a limitation on any giv technology. A method that doubles the sampling ratio witho increasing the circuit speed requirements would be useful offering either improved resolution, e.g., 3.5 bits for third-order modulator, or a doubling of the conversion ra without any reduction in resolution for higher frequen applications.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention double the effective operating rate of any oversampl modulator, without any increase in clock rate or circu speed requirements, in order to improve ADC resolution conversion rate.

The invention contemplates a circuit transformati applicable to any switched capacitor (SO oversampl modulator, regardless of its order, that doubles i effective sampling rate. The circuit transformation consis of adding a second input capacitor and switches to ea integrator operating on alternate clock phases. The switch employed in the circuitry are typically field effe transistor (FET) switches. In addition, each quantizer the network is replaced by two quantizers, again operated opposite clock phases. Alternatively, the quantizers can simply operated at twice the normal rate if feasible for t particular circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

Figure 1 is a schematic diagram of a first-order oversampled modulator; Figure 2 is a schematic diagram of a double-rate oversampled modulator according to the invention;

Figure 3 is a timing diagram showing the clock waveforms for operating the switches in the double-rate oversample modulator shown in Figure 2; Figure 4 is a schematic diagram of a first-orde oversampled double-rate modulator according to the invention'

Figure 5 is a timing diagram showing the clock waveform for operating the switches in the modulator shown i Figure 4; Figure 6 is a schematic diagram of a double-rate second order oversampled modulator according to the invention;

Figure 7 is a schematic diagram of a double-rate third order oversampled modulator according to the invention;

Figure 8 is a schematic diagram of a double-rat oversampled modulator using a single double-rate analog-to digital converter and a single double-rate digital-to-analo converter;

Figure 9 is a timing diagram showing the clock waveform for the modulator shown in Figure 8; Figure 10 is a schematic diagram of a double-rat oversampled modulator using a single double-rate analog-to digital converter but two digital-to-analog converters;

Figure 11 is a schematic diagram of a double-rate third order oversampled modulator using differential amplifier with chopper stabilization for the first stage; and

Figure 12 is a timing diagram showing the cloc waveforms for operating the switches in the modulator shown in Figure 11.

DETAILED DESCRIPTION OF THE INVENTION

Figure 1 shows a simple first-order modulator 10 that switches alternately between clock phases φi and <j>2, using two phase-nonoverlapping clocks. The modulator comprises a stray-free switched capacitor integrator 18 along with an analog-to-digital converter (ADC) 16 and a digital-to-analog converter (DAC) 17.

During clock phase φi, the modulator analog input signal Vi is sampled by an input capacitor 12 as a switch 11 is connected to the input and switch 13 is connected to ground. Also during this clock phase, an operational amplifier 14, acting as a sample and hold circuit due to a feedback capacitor 15 of capacitance C _f , provides a constant signal for ADC 16 to convert to a digital format. The output signal of ADC 16 is supplied to the digital input of DAC 17 so as to provide a quantized analog signal as a feedback signal to integrator 18.

On the subsequent clock phase φ2, switches 11 and 13 alternate to connect input capacitor 12 between the output of DAC 17 and the inverting input of operational amplifier 1 . This causes a charge equal to the difference between the input voltage and the DAC output voltage VQ _AC times the value of the input capacitance Ci to be injected into the operation amplifier feedback capacitor 15. As a result, the operational amplifier output voltage V _Q changes in the discrete time domain according to the following equation:

V ₀ (nT) = V ₀ [ {n-l ) T] + - [V_[ (n-l) T] -V _DAC { (n-l) T] ,

C _f

where n represents the discrete time instant nT (T being th sampling period of the two phase clocks) . Taking the transform of the above equation results in the followin equation:

-- _{Q l} Δ ₇ ,) _ - — Ci Δ_-ι Vi ( Z-) -V-— _AC ( Z) ,

Cf [i-z η

Z being the discrete time frequency variable. The integrato in this configuration therefore integrates the difference o the analog input signal and the DAC output signal in th feedback loop.

At low frequencies, the gain of the integrator is ver high so that the output signal of the modulator approximate the input signal of the loop with little error. Furthermore quantization noise introduced by ADC 16 is attenuated by t loop gain and is thereby attenuated at low frequency a becomes prominent at frequencies where the loop gain is lo The output of ADC 16 is connected to a digital lowpass filt and a decimator (not shown) to attenuate high frequen quantization noise and produce a high resolution digit output signal.

The new double-rate oversampled modulator 20 accordi to the invention is shown in Figure 2 and the switch timi clock phases are shown in Figure 3. The invention applie for the first time, high frequency switched capacit techniques to oversampled modulators. Such techniques ha been used in ladder filters as described by Tat C. Choi a Robert W. Bordersen in "Considerations for High-Frequen Switched-Capacitor Ladder Filters", IEEE Trans, on Circui and Systems. Vol. CAS-27, No. 6, June 1980, pp. 545-552. T technique used in the present invention permits the samp rate to be twice the clock rate.

Referring now to Figure 2, a switched capacit integrator 30 comprises two input switches 21a and 2 connected to alternately sample the analog input volta

during clock phases φi and Φ2, respectively. However, the is a nonoverlapping of the sampling of the analog inp signal, as indicated by the time spacing between the i and clocks in Figure 3. This avoids any overlap of t connection of input capacitors 22a and 22b by switches 2 and 23b, respectively, to the inverting input of operational amplifier 24. Thus, while a feedba capacitor 25 is being charged by one of the input capacitor the other input capacitor is sampling the input voltage. switch 28 is connected to the output of integrator 30 alternately connect the output at the clock rate to L-b ADCs 26a and 26b, L being the quantization level of ea individual ADC and DAC. The outputs of the L-bit ADCs 2 and 26b are connected to an L-bit 2-to-l multiplexer 29 whi provides the L-bit digital output. The L-bit output signa of ADCs 26a and 26b are respectively supplied to L-b DACs 27a and, 27b which, in turn, generate analog feedba voltages to the sampling switches 21a and 21b.

Operation at twice the original speed is achieved by t action of the second set of capacitors and switches, allowi integrator 30 to update its output signal on both clo phases. In addition, the dual ADCs 26a, 26b and du DACs 27a, 27b facilitate quantization to be carried out both clock phases. Matching of the two quantizers is n critical, although each DAC 27a and 27b must have an accura comparable with the required resolution of the oversampl system after decimation and filtering. when this is t case, relative gain and offset errors of the two DACs avera together to determine the overall gain and offset aft decimation. Also, in a preferred embodiment, one bit AD and DACs are used, due to their inherent linearity.

A specific implementation of the double-rate techniq applied to a first-order oversampled modulator 40 is shown Figure 4 for the case of a one-bit quantizer, and t associated clock waveforms are shown in Figure 5. Elemen

which are identical to those of Figure 2 are identified by the same reference numerals in Figure 4. The one-bit ADCs 41a and 41b respectively comprise operational amplifiers 42a and 42b having input capacitors 43a and 43b alternately connected to the output of operational amplifier 24 and ground by switches 44a and 44b, respectively. Feedback loops between the outputs and th negative inputs of operational amplifiers 42a and 42b ar provided with switches 45a and 45b which are alternatel opened and closed. Thus, the ADCs 41a and 41b comprise auto zeroed comparators . The outputs of the operationa amplifiers 42a and 42b are connected by respective invertin amplifiers 46a and 46b to multiplexer 29 and to respectiv DACs 47a and 47b. Each of DACs 47a and 47b is just a single pole, double-throw (SPDT) switch that connects to either th reference voltage V _ref or to -V _re f.

The two-phase switching sequence of the auto-zeroe comparators adds a one-half cycle delay to the feedback loop that is necessary for stable operation of the modulator. Th two-level DACs 47a and 47b are advantageous since mismatch i their levels can only introduce an offset error and canno add any nonlinearity. Offset can usually be tolerated an often calibrated out; however, non-linearity is a sever problem to overcome once introduced. Those skilled in th art will recognize that a dither signal is needed for th case of a first-order modulator, but this detail is no indicated in Figures 1 or 4.

To demonstrate that this double-rate circuit techniqu is applicable to virtually any oversampled network, secon and third-order implementations are shown in Figures 6 and 7 respectively.

Figure 6 shows a double-rate second-order oversampl modulator 60 which incorporates the modulator 20 of Figure preceded by an additional double-rate integrator substantially identical to integrator 30. The input

second-order modulator 60 is via switches 61a and 61b integrator 31 which alternately sample the input anal voltage and the output signal of the L-bit DACs 27a and 27 respectively. The sampled analog voltage charges inp capacitors 62a and 62b when the capacitors are connected ground via switches 63a and 63b, respectively. Alternatel the capacitors are connected to the inverting input of second operational amplifier 64. The output of operation amplifier 64 is alternately sampled by switches 21a and 21b. The aforementioned application Serial No. 07/505,384 directed to a third-order oversampled modulator. Figure shows a modification of that modulator to form a double-ra third-order oversampled modulator 70. This 'modulat incorporates the structure of double-rate second-ord modulator 60 of Figure 6 with the addition of a double-ra first-order modulator 21 substantially identical modulator 20 of Figure 2, and therefore like referen numerals identify identical elements in the two figures. Figure 7, modulator 21 includes a switched capacit integrator 32 having switches 71a and 71b which alternate sample the output signal of integrator 30, and the sampl output signal is alternately applied to the inverting inp of a third operational amplifier 74. The output signal integrator 32 is supplied via a switch 78 to M-bit ADCs 7 and 76b, the output signals of which are supplied to an M-b 2-to-l multiplexer 79. The output signals of M-bit ADCs 7 and 76b are also supplied to corresponding M-bit DACs 7 and 77b, the outputs of which are alternately connected input capacitors 72a and 72b by switches 71a and 71 respectively. Switches 73a and 73b function analogously switches 23a and 23b, respectively, in modulator 20 Figure 2.

The output signal of M-bit multiplexer 79 is multipli by a gain factor G in a digital multiplier 81. The outp signal of multiplier 81 is supplied to a digit

subtractor 82. The output signal of L-bit multiplexer 29 is delayed one cycle by a delay register 83, and the output signal of this register is supplied to the subtrahend input of digital subtractor 82. The difference output signal of digital subtractor 82 is supplied to a pair of cascaded digital differentiators 84, each comprised of a one-cycle delay register 85 and a digital subtractor 86. Finally, the output signals of delay register 83 and the second of cascaded differentiators 84 are summed in a digital adder 87 to produce the digital output signal of modulator 70.

The circuit elements 81 to 87 comprise a digita canceler. That is, the difference between the two digita output signals from modulators 60 and 21 is exactly equal t minus the quantization noise of second-order modulator 60. double differentiated signal from cascaded differentiators 8 is added to the digital output signal of second-orde modulator 60 to effect the cancellation of the quantizatio noise of modulator 60. A more detailed description of thi canceler is set forth in the aforementioned Ribne application Serial No. 07/505,384 filed April 6, 1990. Thi is but one form of digital canceler and other implementation are possible.

In both Figures 6 and 7, L-bit quantizers are shown fo generality; however, it will be understood by those skille in the art that for the case L=l (i.e., l-bit quantization) the auto-zeroed comparator circuit and single-pole double throw switch scheme shown in Figure 4 would be substitute for each ADC and DAC combination as shown in Figures 6 and 7 Also in Figure 7, M-bit ADCs 76a, 76b and M-bit DACs 77a, 77 are employed in the event a different number of bits (or different quantization level) is used in each of the tw cascaded modulators 60 and 70.

Where sufficiently fast quantizers (i.e., ADC and D combination) are available, then double-rate operation can achieved as illustrated in Figure 8 which shows, by way

example, a first-order double-rate oversampled modulator 9 This modulator is similar to that shown in Figure 2, exce for the use of a double-rate L-bit ADC 96 and a double-ra L-bit DAC 97. Use of the double-rate L-bit ADC eliminat need for the 2-to-l multiplexer employed in the modulator Figure 2, the L-bit digital output signal being tak directly from L-bit ADC 96. The clock waveforms for t modulator shown in Figure 8 are shown in Figure 9. Since A 96 and the DAC 97 are operated at double rate, they perfo conversions on both clock phases.

A further variation is introduced in Figure 10 f situations where the ADC is faster than the available DA In this embodiment, a double-rate ADC 96 is used, but a pa of single-rate DACs 97a and 97b are employed in the feedba loops. A multiplexor, illustrated as a switch 9 alternately couples the output of ADC 96 to DACs 97a and 97 It will be understood that operation of the modulator circu shown in Figure 10 is essentially similar to operation of t modulator shown in Figure 2. Also, it will be understo that either of the approaches of Figures 8 and 10 can incorporated in the context of the modulator networks Figures 6 and 7.

Although the modulator components, i.e., t integrators, ADCs and DACs, have so far been illustrated wi single-ended outputs, the third-order sigma delta analog-t digital converter of this invention has been implemented employing a differential signal path using integrators wi differential outputs for improved rejection of power supp noise. This implementation is shown in Figure 11. The network of Figure 11 employs differential amplifie in a manner representative of the circuitry used in a thir order sigma delta oversampled A/D converter network te chip, while Figure 12 illustrates the clock wavefor employed in the circuit of Figure 11. The circuit Figure 11 differs from the single-ended switched-capacit

A/D converter network shown in Figure 7 in that (1) it uses four-phase instead of two-phase clocking, (2) it makes use of a fully-balanced (or differential) signal path for better rejection of spurious power supply noise .and common mode signals, (3) it employs a chopper stabilization circuit for suppression of low frequency operational amplifier noise, (4) it can be operated as a single-ended input circuit even though it is a differential circuit, and (5) it uses double- speed ADCs and single-rate DACs, as in the circuit of Figure 10. Integrators 30', 31' and 32' employed in the circuit of Figure 11 correspond to integrators 30,31, and 32, respectively, in the circuit of Figure 7 but include balanced outputs and balanced inputs. In addition, although not shown in Figure 11, it will be understood that a digital canceler, corresponding to circuit elements 81 to 87 interconnected as shown in Figure 7, is also provided. The circuit shown in Figure 11 represents the circuitry implemented on an integrated circuit chip.

In considering operation of the circuit of Figure 11, the presence of a chopper 200 as part of integrator 31' will be ignored initially by assuming chopper phase ΦCHP is always asserted. A balanced input signal is also assumed. In these circumstances, operation is similar to that of the single- ended circuit of Figure 7; however, the precise phase assignment for sampling and integration is different. The balanced circuit integrates on clock phases φi and 3 an samples during clock phases Φ2 and Φ4, whereas the circuit o Figure 7 performs sampling and integration on both of its clock phases. Operation is similar to that described for th circuit of Figure 7 except that when the input signal i alternately sampled during phases Φ2 and Φ4 by one of tw balanced input pairs of capacitors 201a, 201b and 202a, 202b, the output sides of capacitors 201a and 201b are connecte together through switch Sχo during phase Φ2 and similarly the output sides of capacitors 202a and 202b are connecte

together through switch Sn during phase Φ ₄ , instead of t ground. This connection is made so that only th differential component of the input signal is acquired. common mode signal, if present, would also be sampled i capacitor pairs 201a, 201b and 202a, 202b were switched t ground instead of to each other; however, in th configuration shown, the charge stored on input capacito pairs 201a, 201b and 202a, 202b depends only on th difference between the two input signals, not on thei average value. Similar effects occur with regard to inpu capacitor pairs 203a, 203b and 204a, 204b for the secon stage integrator 30' of the network and input capacito pairs 205a, 205b and 206a, 206b for the third stag integrator 32 of the network. As just described, the output sides of the inpu capacitor pairs for each of the integrator stages would neve be connected to a voltage source or ground, and hence th voltages on each of these capacitors would be arbitrary Similarly, the voltage level at the input to the operationa amplifier receiving a signal from its input capacitors woul be undefined. Therefore, to establish the potential at th output (or right-hand) side of the input capacitors, connection to ground during phases φi and Φ3 is employed whil the input (or left-hand) side of each input capacitor remain connected to the positive and negative reference signals.

Another minor difference from the circuit of Figure 7 i that one-bit DACs 210, 211 and 212 are implemented directl at the input (or left-hand) sides of the input capacito pairs 201a, 201b and 202a, 202b of integrator 31, 203a, 203 and 204a, 204b of integrator 30" and 205a, 205b and 206a 206b, of integrator 32', respectively, instead of b employing L-bit DACs as shown in the network of Figure 6.

The logic for the individual switch positions in DAC 210, 211 and 212, expressed in Boolean algebra, is a follows:

ΦDACPI = φi3'(CMPlΘφcif _N )

ΦDACNI = φi3-( MPΪ®φ _CHW )

Φ _DAC P2 = Φl3' MPl

ΦDACN2 = φi3'C Pl ΦDACPS = φi3'CMP2

ΦDACN3 = Φl3'C P2 where CMPl and CMP2 are the output signals from comparator 216 at the output of second stage integrator 30', as latched by a latch ^* circuit 218, and the output signal from a comparator 226 at the output of third stag integrator 32', as latched by a latch circuit 228, respectively. clock waveforms for the circuit are shown i Figure 12.

In considering the role of the chopper, the MOS (meta oxide semiconductor) switching devices represented by double pole, double-throw (DPDT) chopper switches 200 on either sid of a first operational amplifier 222 perform a periodi reversal of signal polarities at the input and output of th operational amplifier as controlled by the ΦCHP and ΦCH chopper clock signals. Clocks ΦCHP ^nci ΦCHN, illustrated i the waveform drawings of Figure 12, may alternate at any rat that is an integral multiple of the output conversion rate up to a maximum rate of the modulator frequency. Whe clock ΦCHP is high, a noninverting path through operationa amplifier 222 is selected by the chopper at both input an output, while when phase ΦCHN i high, an invertin configuration is produced. Since inversion takes plac simultaneously at both the input and output of t operational amplifier whenever clock ΦCHN s high, there is effect on signals traversing the integrator. However, noi from the operational amplifier itself goes through only t

output switches of the chopper and, as such, alternates i polarity at a rate determined by the frequency of the choppe clocks. This is equivalent to multiplying the noise by periodic square wave signal with an amplitude of ±1, whic amounts to a modulation of the operational amplifier noise u to the frequency of the chopper square wave and all of it harmonics. As a result, the severe low frequency flicker (o 1/f) noise is moved out of the baseband frequency of th modulator. Flicker noise is discussed in R. Gregorian "Analog MOS Integrated Circuits for Signal Processing" Wiley, New York (1986), at pages 500-505, and the discussio therein is hereby incorporated by reference. Subsequen digital filtering by a. digital decimation filter (not show in Figure 11) removes the modulated 1/f noise. In fact chopping at a rate equal to the output rate of the decimatio filter, or a higher integral multiple, places the fundamenta and harmonics of the square wave at the frequencies of th zeros of the decimation filter (if a comb-type filter i used), facilitating removal of the modulated noise. Any mismatch in sizes of the input capacitors and FE switches (which function as transmission gates) can introduc an input error signal that switches between two rando voltage levels as the two pairs of input capacitors perfor their alternate signal-sampling function. to cancel thi error source, a dynamic element matching technique is use whereby the two capacitors comprising each balanced pair o input capacitors are periodically interchanged. This cause error signals due to a mismatch of the aforementioned type t alternate in polarity so as to cancel out after decimation This approach, which is similar to that described in U.S Patent No. 4,896,156 issued to S. Garverick on January 23 1990 for "Switched-Capacitance Coupling Networks fo Differential-Input Amplifiers not Requiring Balanced Inpu Signals" and assigned to the instant assignee, is implemente in the double-rate third-order modulator of Figure 11 i

conjunction with the chopping switches 200 of first integrator 31' . The periodic reversal of input capacitors 201a and 201b requires interchanging of their connections at both left-hand and right-hand terminals . At the right-hand terminals, this is done by direct connection to the inputs of operational amplifier 22; i.e., by bypassing DPDT chopping switch 200 at the input side of amplifier 222. The connectivity is equivalent to using additional cross- coupled DPDT switches (wired like chopping switch 200 at the input side of amplifier 222) in series with the right-hand sides of capacitor pairs 201a, 201b and 202a, 202b. the connection employed in the circuit of Figure 11 has the benefit of not requiring the extra DPDT switches .

On the left-hand side of the input capacitors, periodic reversal is implemented by reversing the polarity of the input signals at capacitors 202a and 202b by logically ANDing the clock Φ ₂₄ signal with the chopping clock signals ΦCHP ^or ΦCHN for input clocks ΦINP a d ΦINN, respectively. In a similar manner, the polarity of the l-bit DAC 210 signal is periodically reversed in synchronization with the chopping signal ΦCHN- This is accomplished by the logical ORing of the ΦCHN clock with the CMPl and CMPlb signals for ΦDACPI ^and ΦDACP2, respectively, as indicated by the above logical equations . In this specific implementation, the output signal of operational amplifier 222 is taken directly from th operational amplifier instead of after the chopping DPD switch 200 coupled to the output of the amplifier. Thi connection is more favorable for operation at fast cloc rates since transients settle faster to this point than afte the chopping DPDT switch 200. However, polarity of th amplifier output signal here alternates periodically due t the chopping signals, whereas on the other side of th chopping switch 200 coupled to the output of the amplifier polarity does not alternate. To compensate for this, inpu

switches 204 to the second integrator 30' also periodical reverse the polarity of the input signal as is done in t first integrator 31'.

While only certain preferred features- of the inventi have been illustrated and described herein, ma modifications and changes will occur to those skilled in t art. It is, therefore, to be understood that the append claims are intended to cover all such modifications a changes as fall within the true spirit of the invention.