Title:
DOUBLE-SIDE POLISHING METHOD AND DOUBLE-SIDE POLISHING DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/141704
Kind Code:
A1
Abstract:
The present invention is a double-side polishing method wherein a semiconductor wafer held by a carrier is sandwiched between an upper surface plate and a lower surface plate, which have polishing pads adhered thereto, respectively, and both the surfaces of the semiconductor wafer are brought into slide-contact with the polishing pads, thereby polishing both the surfaces of the semiconductor wafer at one time. In the method, the polishing is performed such that a thickness A (mm) of the polishing pad adhered to the upper surface plate, and a thickness B (mm) of the polishing pad adhered on the lower surface plate satisfy relationships of 1.0≤A+B≤2.0, and A/B>1.0. Consequently, provided is the double-side polishing method whereby a semiconductor wafer satisfying formula of front Z-height double differentiation (F-ZDD)<0 can be obtained, while suppressing the value of a global back surface-referenced ideal plane/range (GBIR) to be equal to or lower than a request value.
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Inventors:
TANAKA YUKI (JP)
AMAGAI SHIRO (JP)
AMAGAI SHIRO (JP)
Application Number:
PCT/JP2017/003568
Publication Date:
August 24, 2017
Filing Date:
February 01, 2017
Export Citation:
Assignee:
SHINETSU HANDOTAI KK (JP)
International Classes:
H01L21/304
Foreign References:
| JP2016022542A | 2016-02-08 | |||
| JP2014110433A | 2014-06-12 |
Attorney, Agent or Firm:
YOSHIMIYA Mikio et al. (JP)
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