Title:
DUAL CONVERSION GAIN GATE AND CAPACITOR COMBINATION
Document Type and Number:
WIPO Patent Application WO2007016168
Kind Code:
A9
Abstract:
A pixel cell array architecture having a dual conversion gain. A dual conversion gain element is coupled between a floating diffusion region and a respective storage capacitor. The dual conversion gain element having a control gate switches in the capacitance of the capacitor to change the conversion gain of the floating diffusion region from a first conversion gain to a second conversion gain. In order to increase the efficient use of space, the dual conversion gain element gate also functions as the bottom plate of the capacitor. In one particular embodiment of the invention, a high dynamic range transistor is used in conjunction with a pixel cell having a capacitor-DCG gate combination; in another embodiment, adjacent pixels share pixel components, including the capacitor-DCG combination.
Inventors:
MCKEE JEFFREY A (US)
Application Number:
PCT/US2006/029050
Publication Date:
March 27, 2008
Filing Date:
July 26, 2006
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
MCKEE JEFFREY A (US)
MCKEE JEFFREY A (US)
International Classes:
H04N3/15
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