FIELD

The present disclosure relates to voltage regulators, and, more particularly, to a dual mode voltage regulator with reconfiguration capability.

BACKGROUND

System on a Chip (SoC) architectures often require multiple voltage sources (or voltage rails) to meet the variety of operational power requirements imposed by the numerous components in the system such as, for example, various input/output (I/O) sub-systems. Existing solutions typically implement voltage regulators on the platform or circuit board which hosts the SoC integrated circuit (IC). Some of these voltage regulators may be passive regulators while others may be switched mode regulators, depending on the requirements of the sub-system to be powered as well as the voltage available on the platform. This approach, however, consumes circuit board space and increases system complexity and power delivery cost. Additionally, voltage sources may be subject to change (rail voltage reduces) with time. Voltage sources may also vary depending on the sourcing of platform components. The potential for variability in voltage sources, including available line voltage, may limit the type of voltage regulator that can be implemented on the platform or circuit board hosting the SoC integrated circuit (IC).

BRIEF DESCRIPTION OF DRAWINGS

Features and advantages of the claimed subject matter will be apparent from the following detailed description of embodiments consistent therewith, which description should be considered with reference to the accompanying drawings, wherein:

FIG. 1 is a top level system diagram of one exemplary embodiment consistent with the present disclosure;

FIG. 2 is a system diagram of one exemplary embodiment consistent with the present disclosure;

FIG. 3 is a more detailed block diagram of one exemplary embodiment consistent with the present disclosure; and

FIG. 4 is a more detailed block diagram illustrating a dual mode voltage regulator operating in a passive regulator mode consistent with the present disclosure;

FIG. 5 is a more detailed block diagram illustrating a dual mode voltage regulator operating in a switched regulator mode consistent with the present disclosure; and

FIG. 6 is a flowchart of operations of one exemplary embodiment consistent with the present disclosure.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art.

DETAILED DESCRIPTION

By way of overview, the present disclosure is generally directed to methods and apparatus to provide dual mode voltage regulation with reconfiguration capability. The two modes may include a passive regulator mode and a switched regulator mode. An apparatus consistent with the present disclosure may be configured to operate in either mode (passive regulator mode or switched regulator mode) based on parameters of an external select input. The apparatus may include a controller circuit configured to receive a signal from an external select input and selectively couple either the passive regulator or the switched mode regulator between the input voltage port and the output load based on the signal upon a cold boot up of an SoC implementation to improve power conversion efficiency. In some embodiments, the passive regulator circuit may share components with the switched mode regulator circuit including, for example, a power switch and an error amplifier.

A dual mode regulator consistent with the present disclosure may be configured to provide the performance benefits of both a passive regulator and a switched regulator, thereby providing a means of overcoming issues related to changes in line voltage.

FIG. 1 illustrates a top level system diagram 100 of one exemplary embodiment consistent with the present disclosure. A power supply 102 provides input power at a direct current (DC) voltage level to a dual mode voltage regulator 104. The dual mode voltage regulator 104 converts the input DC voltage level to an output voltage level that meets the requirements of load 106 and provides power to load 106 at that converted voltage level. In some embodiments, multiple dual mode voltage regulators 104 may be integrated with a System on a Chip (SoC) architecture where multiple components are integrated on an IC and present loads of varying voltage and power requirements. The multiple dual mode voltage regulator may operate from a common input voltage that is available to the SoC.

FIG. 2 illustrates a system diagram 200 of one exemplary embodiment consistent with the present disclosure. In the illustrated embodiment, the dual mode voltage regulator 104 may include a controller circuit 206, a passive regulator circuit 202, and a switching regulator circuit 204. The controller circuit 206 may be configured to receive a signal from an external select input 208, as will be described in greater detail below, and selectively couple Vin to Vout through either passive regulator circuit 202 or switching regulator circuit 204 based on the signal.

The passive regulator circuit 202 may be a low drop-out (LDO) voltage regulator or other suitable passive voltage regulator. Passive voltage regulators generally operate by controlling current flow from the Vin port to the Vout port through a pass gate which may, for example, be a bipolar junction transistor (BJT) of a field effect transistor (FET). The gating signal for the pass gate may be derived from a differential amplifier (or error amplifier) that monitors the difference between Vout and a desired reference voltage Vref. Passive voltage regulators are typically capable of operating under conditions of reduced voltage differential between Vin and Vout, but they suffer from decreasing power conversion efficiency (the ratio of power out to power in) as the difference between Vin and Vout increases.

The switching regulator circuit 204 may be a buck voltage regulator or other suitable switching mode voltage regulator. Switching mode voltage regulators generally offer increased power conversion efficiency at higher load currents. Switching mode voltage regulators operate by switching current provided by the input power supply on and off at periodic intervals with a duty cycle (or pulse width modulation) that results in a desired voltage level conversion. For example, a 50 percent duty cycle may provide an output voltage to the load that is approximately one half of the input power supply line voltage. The pulse width modulated signal is typically processed by a filter at the output load, for example an inductor-capacitor network, to provide a DC output voltage waveform. The current switching may be performed by one or more switches, for example BJTs or FETs. The modulation rate or duty cycle may be dynamically adjusted by monitoring the difference between Vout and a desired reference voltage Vref.

Although it may be possible to improve the power conversion efficiency of switching mode voltage regulators operating at reduced load currents, these techniques increase circuit complexity and cost.

FIG. 3 illustrates a more detailed block diagram 300 of one exemplary embodiment consistent with the present disclosure. The dual mode voltage regulator 104 is shown providing output voltage to load 106. The controller circuit 206 may be configured to receive a signal from the external select input 208. In one embodiment, the external select input 208 may include a hard-wired strap (i.e. an input connected to ground, connected to a common connector voltage Vcc, or the input may be floating). In other embodiments, the external select input 208 may include a controlling signal having basic functionality of, for example, an external system controller.

The signal from the external select input 208 may include parameters associated with the external select input 208, such as, for example, a voltage reference of the external select input 208, a ratio of the output voltage Vout to the input voltage Vin, and/or a load current. The controller circuit 206 is coupled to error detection / PWM generation circuit 304, timing generator / gate driver 302, error amplifier 306, selection circuit 308, and upper and lower power switches 310, 312, the operation of which will be explained in greater detail below. The error amplifier 306 provides feedback based on the difference between the converted output voltage and the desired output voltage as represented by a provided reference voltage Vref. The upper and lower power switches 310, 312 may be BJTs, FETs or other suitable types of power switches. The upper power switch 310 may also serve as a pass gate during passive (LDO) mode operation. An inductor-capacitor filter network 314, provided to smooth the output voltage, is also shown.

As previously described, the controller circuit 206 may configure the dual mode voltage regulator 104 to operate in either an LDO (or passive) mode or a Buck (or switched) mode. FIGS. 4 and 5 are detailed block diagrams 400, 500 illustrating the dual mode voltage regulator 104 operating in an LDO (or passive) mode and Buck (or switched) mode, respectively. In particular, the control loops for each mode are illustrated in bold, wherein components and pathways not in use during either of the modes are in phantom. Upon receiving and determining parameters of the external selection input 208, the controller circuit 206 may advantageously configure the regulator 104 to operate in the mode best suited for the operating condition on a cold boot up of an SoC implementation.

For example, in the event that the parameters of the external select input 208 indicate that the load current is measured below a pre-determined threshold, the controller circuit 206 may configure the regulator 104 to operate in the LDO (or passive) mode rather than the Buck (or switched) mode. As another example, if the parameters of the external select input 208 indicate that the ratio of load voltage to input (or line) voltage is below a second pre-determined threshold, a higher power conversion efficiency may be obtained by configuring the regulator 104 to operate in the LDO mode rather than the Buck mode. In some embodiments, the controller circuit 206 may determine that a system clock is not present, as may occur during a system boot, in which case the controller may configure the regulator to operate in the LDO mode.

Additionally, the controller circuit 206 may configure the regulator 104 to operate in either the LDO or Buck modes based on a ratio of output voltage Vout to input voltage Vin. For example, in the event that the parameters of the external select input 208 indicate that the ratio of output voltage Vout to input voltage Vin is below a pre-determined threshold, the controller circuit 206 may configure the regulator 104 to operate in the Buck mode. As another example, in the event that the ratio of output voltage Vout to input voltage Vin is above a pre-determined threshold, the controller circuit 206 may configure the regulator 104 to operate in the LDO mode. Additionally, the controller circuit 206 may configure the regulator 104 to operate in either the LDO or Buck modes based on determining a predicted load current of the external select input 208. For example, in the event that the predicted load current of the external select input 208 is below a pre-determined threshold, the controller circuit 206 may configure the regulator 104 to operate in the LDO mode.

The error detection / PWM generation circuit 304 may be employed during Buck mode operation to compare the output voltage Vout to the reference voltage Vref and adjust the PWM to attempt compensate for any difference. The PWM signal may then be employed by the timing generator / gate driver circuit 302 to generate the timing signals corresponding to mark and space times that will drive the upper and lower power switches 310, 312. The selection circuit 308 determines, based on the current mode configuration, whether the signals from timing generator / gate driver circuit 302 will drive the power switches (in Buck mode) or whether the error amplifier 306 output will drive the upper power switch 310 as a pass gate (in LDO mode).

The controller circuit 206 may de-power some or all components that are exclusively associated with the mode that is not in use to reduce power dissipation. For example, as shown in FIG. 4, during operation in an LDO mode, the controller circuit 206 may be configured to de- power the error detection / PWM generation circuit 304, timing generator / gate driver 302, and/or lower power switch 312. Additionally, as shown in FIG. 5, during operation in a Buck mode, the controller circuit 206 may be configured to de-power the error amplifier 306. Some components may be shared between modes, however, such as, for example, the upper power switch 310 and the error amplifier 306.

In some embodiments, the controller circuit 206 may be configured to power up in LDO mode as a default, thus enabling power up in the absence of a system clock as may occur during a boot up of an SoC implementation.

It should be noted that, for the purposes of illustration, the control loops of the LDO and Buck modes of FIGS. 4 and 5, respectively, are shown independent. In some embodiments, some components, such as the error amplifier 306, may be redeployed between both modes, thereby reducing silicon overhead.

FIG. 6 illustrates a flowchart of operations 600 of one exemplary embodiment consistent with the present disclosure. At operation 610, parameters of an external select input are determined. The parameters may include, for example, a voltage reference of the external select input, a ratio of the output voltage Vout to the input voltage Vin, and/or a load current. At operation 620, one of a passive voltage regulator or a switching regulator is selectively coupled between an input voltage port and an output voltage port, based on the determining. In some embodiments components may be shared between the passive voltage regulator and the switching voltage regulator.

While FIG. 6 illustrates method operations according various embodiments, it is to be understood that in any embodiment not all of these operations are necessary. Indeed, it is fully contemplated herein that in other embodiments of the present disclosure, the operations depicted in FIG. 4 may be combined in a manner not specifically shown in any of the drawings, but still fully consistent with the present disclosure. Thus, claims directed to features and/or operations that are not exactly shown in one drawing are deemed within the scope and content of the present disclosure.

Additionally, operations for the embodiments have been further described with reference to the above figures and accompanying examples. Some of the figures may include a logic flow. Although such figures presented herein may include a particular logic flow, it can be appreciated that the logic flow merely provides an example of how the general functionality described herein can be implemented. Further, the given logic flow does not necessarily have to be executed in the order presented unless otherwise indicated. In addition, the given logic flow may be implemented by a hardware element, a software element executed by a processor, or any combination thereof. The embodiments are not limited to this context.

Embodiments of the methods described herein may be implemented in a system that includes one or more storage mediums having stored thereon, individually or in combination, instructions that when executed by one or more processors perform the methods. Here, the processor may include, for example, a system CPU (e.g., core processor) and/or programmable circuitry. Thus, it is intended that operations according to the methods described herein may be distributed across a plurality of physical devices, such as processing structures at several different physical locations.

The storage medium may include any type of tangible medium, for example, any type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), digital versatile disks (DVDs) and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, magnetic or optical cards, or any type of media suitable for storing electronic instructions. As described herein, various embodiments may be implemented using hardware elements, software elements, or any combination thereof. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth.

"Circuitry", as used in any embodiment herein, may comprise, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry.

Certain embodiments described herein may be provided as a tangible machine-readable medium storing computer-executable instructions that, if executed by the computer, cause the computer to perform the methods and/or operations described herein. The tangible computer- readable medium may include, but is not limited to, any type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD- RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic and static RAMs, erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), flash memories, magnetic or optical cards, or any type of tangible media suitable for storing electronic instructions. The computer may include any suitable processing platform, device or system, computing platform, device or system and may be implemented using any suitable combination of hardware and/or software. The instructions may include any suitable type of code and may be implemented using any suitable programming language.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. The features, aspects, and embodiments are susceptible to combination with one another as well as to variation and modification, as will be understood by those having skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications.