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Patent Searching and Data


Title:
DYNAMIC METROLOGY SCHEMES AND SAMPLING SCHEMES FOR ADVANCED PROCESS CONTROL IN SEMICONDUCTOR PROCESSING
Document Type and Number:
WIPO Patent Application WO2002103778
Kind Code:
A3
Abstract:
A system, methods and mediums are provided for dynamic adjustment of sampling plans in connection with a wafer (or other device) to be measured. A sampling plan provides information on specific measure points within a die, a die being the section on the wafer that will eventually become a single chip after processing. There are specified points within the die that are candidates for measuring. The stored die map information may be retrieved and translated to determine the available points for measurement on the wafer. The invention adjusts the frequency and/or spatial resolution of measurements when one or more events occur that are likely to indicate an internal or external change affecting the manufacturing process or results. The increase in measurements and possible corresponding decrease in processing occur on an as-needed basis. The dynamic metrology plan adjusts the spatial resolution of sampling within-wafer by adding, subtracting or replacing candidate points from the sampling plan, in response to certain events which suggest that additional or different measurements of the wafer may be desirable. Where there are provided a number of candidate points in the die map in the area to which points are to be added, substracted, or replaced, the system can select among the points. Further, the invention may be used in connection with adjusting the frequency of wafer-to-wafer measurements.

Inventors:
SHANMUGASUNDRAM ARULKUMAR P
SCHWARM ALEXANDER T
Application Number:
PCT/US2002/019116
Publication Date:
December 11, 2003
Filing Date:
June 17, 2002
Export Citation:
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Assignee:
APPLIED MATERIALS INC (US)
International Classes:
B24B37/04; B24B49/03; B24B49/18; B24B53/007; G05B19/00; G05B19/19; G05B19/418; H01L21/00; H01L21/02; H01L21/66; H01L21/3105; (IPC1-7): H01L21/66
Domestic Patent References:
WO1999059200A11999-11-18
WO2001052319A12001-07-19
WO2001011679A12001-02-15
WO2001080306A22001-10-25
WO2000054325A12000-09-14
Foreign References:
US6002989A1999-12-14
US5546312A1996-08-13
Other References:
WILLIAMS R ET AL: "Optimized sample planning for wafer defect inspection", SEMICONDUCTOR MANUFACTURING CONFERENCE PROCEEDINGS, 1999 IEEE INTERNATIONAL SYMPOSIUM ON SANTA CLARA, CA, USA 11-13 OCT. 1999, PISCATAWAY, NJ, USA,IEEE, US, PAGE(S) 43-46, ISBN: 0-7803-5403-6, XP010360683
EL CHEMALI C AND AL: "Multizone uniformity control of a chemical mechanical polishing process utilizing a pre- and postmeasurement strategy", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY: PART A, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 18, no. 4, pt 1-2, July 2000 (2000-07-01), pages 1287 - 1296, XP002217674, ISSN: 0734-2101
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