Title:
DYNAMIC REAL-TIME DELAY CHARACTERIZATION AND CONFIGURATION
Document Type and Number:
WIPO Patent Application WO/2010/030688
Kind Code:
A3
Abstract:
In mask programmable integrated circuit, such as a structured ASIC, a delay chain provides a delay that is set by a mask programmable switch. The delay chain receives an input to allow the delay mask programmed delay to be overridden using a JTAG controller. This allows testing of different delays. The input may also be provided by a fuse block, so that the fuse block can override the mask programmable switch, thus allowing a delay to be changes after mask programming.
Inventors:
TAN JUN PIN (MY)
KOAY WEI YEE (MY)
ANG BOON JIN (MY)
WONG CHOONG KIT (MY)
SOH GUANG SHENG (MY)
KOAY WEI YEE (MY)
ANG BOON JIN (MY)
WONG CHOONG KIT (MY)
SOH GUANG SHENG (MY)
Application Number:
PCT/US2009/056389
Publication Date:
June 10, 2010
Filing Date:
September 09, 2009
Export Citation:
Assignee:
ALTERA CORP (US)
TAN JUN PIN (MY)
KOAY WEI YEE (MY)
ANG BOON JIN (MY)
WONG CHOONG KIT (MY)
SOH GUANG SHENG (MY)
TAN JUN PIN (MY)
KOAY WEI YEE (MY)
ANG BOON JIN (MY)
WONG CHOONG KIT (MY)
SOH GUANG SHENG (MY)
International Classes:
G11C7/22; G11C8/00; H03L7/00
Foreign References:
| US6219288B1 | 2001-04-17 | |||
| US7098691B2 | 2006-08-29 | |||
| US6269462B1 | 2001-07-31 | |||
| US20040113668A1 | 2004-06-17 |
Other References:
See also references of EP 2329497A4
Attorney, Agent or Firm:
GALLAGHER, Peter, A. et al. (P.O. Box 70250Oakland, CA, US)
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