EFFICIENT MULTIPLICATION SEQUENCE FOR LARGE INTEGER OPERANDS WIDER THAN THE MULTIPLIER HARDWARE

Title:

EFFICIENT MULTIPLICATION SEQUENCE FOR LARGE INTEGER OPERANDS WIDER THAN THE MULTIPLIER HARDWARE

Document Type and Number:

WIPO Patent Application WO2004095234

Kind Code:

A3

Abstract:

A method of operating a multiplication circuit (21) to perform multiply-accumulate operations on multi-word operands is characterized by an operations sequencer (23) that is programmed to direct the transfer of operand segments between RAM (15) and internal data registers (27; RX, RY, RZ, RR) in a specified sequence. The sequence (e.g., Figs. 5A-5C) processes groups of two adjacent result word-weights (columns), with the multiply cycles within a group proceeding in a zigzag fashion by alternating columns with steadily increasing or decreasing operand segment weights. In multiplier embodiments having additional internal cache registers (C_A0, C_ Al, C_B0, C_B1, C_B2), these store frequently used operand segments so they aren't reloaded from memory multiple times. In this case, the sequence within a group need not proceed in a strict zigzag fashion, but can jump to a multiply operation involving at least one operand segment stored in a cache.

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Inventors:

DUPAQUIS VINCENT
PARIS LAURENT

Application Number:

PCT/US2004/008715

Publication Date:

November 03, 2005

Filing Date:

March 22, 2004

Export Citation:

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Assignee:

ATMEL CORP (US)

International Classes:

G06F7/52; G06F9/302; G06F9/32; G06F9/38; (IPC1-7): G06F7/52

Foreign References:

US5457804A	1995-10-10
US4893268A	1990-01-09

Other References: