Title:
EFFICIENT ZERO KNOWLEDGE PROOF ACCELERATOR AND METHOD
Document Type and Number:
WIPO Patent Application WO/2023/108422
Kind Code:
A1
Abstract:
An efficient zero knowledge proof accelerator. A hardware carrier having high computing power and high efficiency can be provided for zero knowledge proof calculation; and a fine-grained pipeline architecture is applied to a multi-scalar multiplication method, and by means of the architecture, a plurality of elliptic curve point addition architectures can be integrated into one large-number modular multiplication hardware circuit without increasing the area of a chip, that is, pipeline calculation acceleration can be performed on an elliptic curve point addition calculation only by means of one large-number modular multiplication hardware circuit. Moreover, a plurality of large-number modular multiplication hardware circuits are further integrated, such that parallel acceleration can be performed on a plurality of elliptic curve point addition calculations. Therefore, compared with the prior art, the method is more flexible, and is applicable to ASICs and FPGAs of different scales.
Inventors:
YANG YONGKUI (CN)
LU ZHENYAN (CN)
YU ZHIBIN (CN)
LU ZHENYAN (CN)
YU ZHIBIN (CN)
Application Number:
PCT/CN2021/137950
Publication Date:
June 22, 2023
Filing Date:
December 14, 2021
Export Citation:
Assignee:
SHENZHEN INST OF ADV TECH CAS (CN)
International Classes:
G06F7/72
Foreign References:
| US20160149704A1 | 2016-05-26 | |||
| CN111373694A | 2020-07-03 | |||
| CN106888088A | 2017-06-23 | |||
| CN102306091A | 2012-01-04 |
Attorney, Agent or Firm:
BEIJING CHENGHUI LAW FIRM (CN)
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