ELECTRIC CIRCUIT FOR PREVENTING INTEGRATED CIRCUITS FROM ATTACKS

FIELD OF THE INVENTION

The invention relates to an electric circuit particularly for preventing security relevant integrated circuits from attacks according to the preamble of claim 1.

BACKGROUND OF THE INVENTION

Integrated circuits are known in the prior art especially as integrated circuits of so called smart cards or chip cards as smart card chips containing security relevant or confidential information. Such confidential information may be a secret encryption key or data to identify the user or owner of the smart card or the like.

Since such data are security relevant, such integrated circuits are within the scope of illegal attacks from third parties not authorized to get such information legally in order to get possession of such secret information to start illegal actions based on the availability of such secret information. For example such integrated circuits are used for smart cards for identification or to allow access to certain protected facilities or to allow money transactions.

Therefore integrated circuits are treated by certain illegal actions out of specifications of the integrated circuit like high voltage, high temperature, different clock rate, flash light or something else in order to disturb the functionality of such integrated circuits to get access to the secret information. The basic idea of such treatment is to disturb the usual functionality of the integrated circuit to create an uncontrolled operational status of the circuit to allow uncontrolled access to the secret data.

Known smart cards contain sensor devices to detect the above described attacks like temperature sensors, voltage sensors, frequency sensors or light sensors. In case a sensor detects an unusual status of the integrated circuit which may be triggered by an attack a reset of the integrated circuit will be initiated in order to stop the unusual and uncontrolled status of the integrated circuit. Such a reset starts the boot sequence of the integrated circuit to restart the functionality of the circuit.

Therefore such attacks have to be applied very often to be successful and the frequency of such attacks is one of the keys of success since such attacks may be applied after a reset again. Additionally a reset takes almost 100 micro seconds and after such a short reset time the circuit is available for the next attacking process.

Accordingly it is possible to deactivate the circuit for a certain period of time to prevent the circuit from a periodically applied attack. This deactivation can be realized

using a memory cell which is able to store one bit of information for a certain period of time without supply voltage. This prevents the integrated circuit from at least some periodically applied attacks.

WO 2007/049181 Al discloses such a circuit allowing to store one bit of information for a certain period of time.

OBJECT AND SUMMARY OF THE INVENTION

A disadvantage of the prior art is, that the bit cannot be cleared intentionally once it is programmed. Object of the invention is to create the possibility of an intentional clearing of a latch like in WO 2007/049181 Al without loosing significant hold time of the information.

The above mentioned problems will be solved using an electric circuit containing the features of claim 1.

According to the invention the objects of the invention are solved using an electric circuit especially for preventing security relevant integrated circuits from attacks containing a memory cell consisting of a diode and a capacitor, wherein the capacitor is connectable firstly with the first diode and secondly with a predetermined potential and a second diode is connectable to mass potential and to the first diode and/or to the capacitor.

According to a preferred embodiment of the invention it is of advantage that the diode is realized as a pnp-transistor allowing a clearing of a programmed memory cell.

According to one embodiment of the invention it is of advantage the circuit is manufactured in CMOS-technology.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the invention will be apparent from the following description of an exemplary embodiment of the invention with reference to the accompanying drawings, in which:

Fig. 1 shows a schematic diagram of an electronic device; Fig. 2 shows a schematic diagram of an electronic device; Fig. 3 shows a schematic diagram of an inventive device; and

Fig. 4 shows a schematic diagram of an inventive device.

DESCRIPTION OF EMBODIMENTS

Figure 1 shows a schematic diagram of an electronic device 1 to prevent an integrated circuit 2 from applied attacks. The device 1 contains a capacitor 12 and a diode 10 with low leakage rate. The capacitor 12 can be charged very quickly via the diode 10, where the charging process can be interpreted as programming of the circuit. The capacitor 12 loses its charge very slowly only during a discharging process.

In a preferred embodiment of a memory cell of the integrated circuit 2 the cell is produced using a standard CMOS process including a p-substrate. A p+/nwell transition zone then produces the diode 10. If the capacitor 12 is connected to ground according to figure 1 this leads to a p-/nwell diode 11 additionally to the p+/nwell diode 10. This additional diode 11 contributes to the discharging of the capacitor 12 of the integrated circuit 2. Reference sign 14 designates the memory port and 13 the program input of the circuit 2. According to figure 2 showing an alternative embodiment the capacitor 22 is connected to a fixed voltage level of the supply port 25 having a supply voltage level being positive compared to the ground level. According to this circuitry of figure 2 the diode 21 no longer contributes to the discharging of the capacitor 22 keeping the holding time of the capacitor 22 on an extended level, that means the holding time is very long compared to the holding time of the embodiment according to figure 1. Reference sign 24 designates the memory port and 23 the program input of the circuit.

The two diodes 20, 21 are defining a bipolar pnp-transistor 30 according to figures 3 and 4. This transistor 30 has a low current amplification but can be used as a device for discharging a capacitor 31. Therefore the positive voltage source 34 connected to the capacitor 31 has to be switchable such that the voltage supplied may be changed.

Figure 3 shows a further embodiment of the invention. The programming of the capacitor 31 will be realised by switching the voltage source to the voltage source of the chip of the circuit and the basis 32 of the transistor will be switched to the voltage potential of 0 V. Accordingly the capacitor 31 or the connection port or memory port 33 will be charged negatively via the collector-basis diode of the transistor 30.

During a reading process the voltage of the device will be switched such that the basis 32 and the power supply terminal 34 are switched to power supply potential. The connection port 33 will follow that change capacitively. In case the connection port is connected to the gate of a pmos-transistor while the source of the pmos-transistor is connected to the supply potential the transistor will not supply a current if the capacitor is

discharged. In case the capacitor is sufficiently charged the transistor opens and supplies a respective current.

In order to discharge the capacitor 31 , the capacitor 31 will be disconnected from port 34 and therefore from the voltage supply source and the capacitor will be connected to ground or mass potential instead. In case of a programmed cell the connection port 33 will follow capacitively to a negative potential. As soon as the pnp-transistor opens the connection port 33 will be discharged to mass potential and the capacitor 31 loses its charge. To open the pnp-transistor the basis 32 has to be at negative potential too. Since the capacity of capacitor 31 is small, a small collector current is needed to discharge the capacitor and therefore the potential of the basis 32 have to be only slightly below mass potential. This may be realised via an additionally provided coupling capacitor at the basis 32. The basis 32 will be connected to mass potential and the coupling capacitor will be charged to supply voltage level. After the capacitor has been charged the basis will be disconnected from mass potential and a negative edge of the coupling capacitor will lower the potential of the basis below mass potential and the capacitor 31 will be discharged and memory content will be deleted.

In case a single pulse of an erasing process is not sufficient to delete all the stored information, it is possible to apply the erasing process several times.

The embodiment of figure 3 reveals the advantage that the holding time of the memory cell is almost unchanged compared to the holding time of the memory cell of figure 2. Additionally the holding time of the memory cell has been increased compared to the holding time of the memory cell according to figure 1 since there is preferably only one diode implemented creating a leakage current. In case of a bipolar transistor the needed chip surface is almost the same compared to the needed chip surface in case of a diode since a parasitic bipolar transistor is besides his low current amplification still sufficient.

According to the embodiment of figure 4 showing a transistor in CMOS- technology A p-doped substrate 40 is used containing a n-doped area as basis 41. The basis 41 contains a n-doped connection port 42 and a p-doped collector 43 realising the pnp- transistor in the design of figure 3 in CMOS-technology.

References

1. device

2. circuit 10 diode

11 diode

12 capacitor

13 program input

14 memory port 20 diode

21 diode

22 capacitor

23 program input

24 memory port 25 supply port

30 transistor

31 capacitor

32 basis

33 memory port 34 supply terminal

40 p-doped substrate

41 basis

42 connection port

43 collector