TECHNICAL FIELD

[0001] The present disclosure generally relates to brain stimulation, and particularly, to a modular electrical system for stimulation of brain with simultaneous electroencephalography (EEG) recording and electrical impedance tomography (EIT) Imaging.

BACKGROUND ART

[0002] Transcranial direct current stimulation (tDCS) is a non-invasive brain stimulation method that can be used in cognitive and clinical protocols in order to modulate neural activity. Although some macro effects are known, the underlying mechanisms are still not clear. tDCS in combination with electroencephalography (EEG) can lead to understanding these mechanisms from neural point of view. For example, in US patents 6230049, 8239030, and 8660650 disclose tDCS methods in combination with EEG. However, simultaneous tDCS- EEG still remains challenging because of the artifacts that affect the recorded signals. For example, simultaneous EEG recording using the electrical brain stimulation may increase the possibility of saturation of EEG electrodes within the range of stimulating electrodes (anode or cathode).

[0003] Previous studies have pointed to the after-effects of tDCS on both motor and cognitive performance, and appear to be potential for using tDCS in a variety of clinical applications. However, little is known about the real-time effects of tDCS on rhythmic cortical activity in humans due to technical challenges of simultaneously obtaining electrophysiological data during ongoing stimulation. There is, therefore, a need for a device for simultaneously acquiring electrophysiological data during brain stimulation using high-resolution EEG.

SUMMARY OF THE DISCLOSURE

[0004] This summary is intended to provide an overview of the subject matter of the present disclosure, and is not intended to identify essential elements or key elements of the subject matter, nor is it intended to be used to determine the scope of the claimed implementations. The proper scope of the present disclosure may be ascertained from the claims set forth below in view of the detailed description below and the drawings. [0005] In one general aspect, the present disclosure describes a circuit for electrical stimulation of a brain, the circuit includes a plurality of electrical stimulators, a plurality of electrodes, a crossbar switch, and a processing unit. Each of the plurality of electrical stimulators may be configured to generate an electrical signal. The crossbar switch may include a plurality of individual switches. The processing unit may be configured to provide a connection between at least one of the plurality of electrical stimulators and a first electrode of the plurality of electrodes through an individual switch of the plurality of individual switches by turning on the individual switch.

[0006] The above general aspect may include one or more of the following features. In an embodiment, the circuit may further include a plurality of transceiver modules. The plurality of transceiver modules may include a first transceiver module. In an exemplary embodiment, the first transceiver module may include an input node PI, an input node P2, and an output node 01. Input node PI may be connected to a second electrode of the plurality of electrodes. Input node P2 may be connected to a third electrode of the plurality of electrodes. Output node 01 may be connected to the processing unit. In an embodiment, the processing unit may be configured to control data transfer through the plurality of transceiver modules. The transceiver module may be configured to receive data from the second electrode and the third electrode. In another embodiment, the first electrode may be the same as the second electrode.

[0007] In an exemplary embodiment, the circuit may further include an adder module. The adder module may be configured to receive data from an output node DRL1 of the first transceiver module and receive data from an output node DRL2 of a second transceiver module of the plurality of transceiver modules. In an embodiment, a sum of data on output node DRL1 and data on output node DRL2 may be loaded to an output node of the adder module.

[0008] In an embodiment, the first transceiver module may further include a DC canceller module, an echo canceller module, a first band-pass filter, a second band-pass filter, a differential amplifier, an amplifier, an anti-aliasing filter, an analog-to-digital converter (ADC), and an output node OUT. In an exemplary embodiment, the DC canceller module may be connected to input node PI through a buffer B2 and a switch S I. Switch SI may be controlled by the processing unit. The DC canceller module may be configured to suppress DC data of input node PI. In an embodiment, the echo canceller module may be connected to input node PI through a buffer B3 and a switch S2. Switch S2 may be controlled by the processing unit. The echo canceller module may be configured to suppress echoes of AC data of the input node PI. In an exemplary embodiment, the first band-pass filter may be connected to input node PI through a buffer B l and a switch S 10. Switch S 10 may be controlled by the processing unit. Outputs of the DC canceller module and the echo canceller module may be connected to an input node of the band-pass filter. In an embodiment, the second band-pass filter may be connected to input node P2 through a switch S I 1. Switch S l l may be controlled by the processing unit. In an exemplary embodiment, the differential amplifier may include a first differential input node, a second differential input node, a differential output node, and a differential ground node. In an embodiment, the first differential input node may be connected to an output of the first band -pass filter. The second differential input node may be connected to an output of the second band-pass filter. The differential ground node may be connected to an output node DRL1. In an exemplary embodiment, the differential amplifier may be configured to load an amplification of a difference between data on the first differential input node and data on the second differential input node to the differential output node. In an embodiment, the amplifier may be configured to amplify data of the differential output node. The anti-aliasing filter may be connected to the amplifier output. The analog -to-digital converter (ADC) may be connected to an output of the anti-aliasing filter. Output node OUT may be connected to an output of the ADC.

[0009] In an exemplary embodiment, an electrical stimulator of the plurality of electrical stimulators may include a power supply, a digital to analog converter (DAC), a current source, a voltage source, a node XI, and a node X2. In an embodiment, the DAC may be configured to generate an amplitude and a frequency of the electrical signal. The current source may br connected to an output node of the DAC. The voltage source may be connected to the output node of the DAC. Node XI may be connected to the current source through a voltage/current limiter and a switch SB 1, and may be connected to the voltage source through the voltage/current limiter and a switch SB2. In an exemplary embodiment, the voltage/current limiter and switches SB 1 and SB2 may be controlled by the processing unit. Node X2 may be connected to the power supply.

[0010] In an embodiment, the processing unit may be configured to provide a digital amplitude and a digital frequency of the electrical signal to the DAC. In an exemplary embodiment, the power supply may include an isolated DC power supply. [0011] In an exemplary embodiment, the electrical stimulator may further include a digital data isolator. The digital data isolator may be configured by the processing unit to provide a digital amplitude and a digital frequency of the electrical signal to the DAC.

[0012] In an embodiment, the circuit may further include an amplification module. The amplification module may include a filter, an amplifier, and analog to digital converter (ADC). In an exemplary embodiment, the filter, the amplifier, and the ADC may be connected in series. The amplification module may be configured to provide a path between the first electrode and an input of the processing unit.

[0013] In an exemplary embodiment, the processing unit may be further configured to calculate an electrical impedance by measuring voltage and current values of the first electrode through the amplification module. In an embodiment, the plurality of electrodes may include an electroencephalography (EEG) electrode connected to a head of a patient.

[0014] In another general aspect, the present disclosure is directed to a circuit for electrical stimulation of a brain. The circuit includes a differential amplifier, an electrical stimulator, and a processing unit. In an embodiment, the differential amplifier may be configured to amplify a difference between data on a node PI and a node P2. The electrical stimulator may be configured to load an electrical signal on node PI. The processing unit may be configured to generate an amplitude and a frequency of the electrical signal. In an exemplary embodiment, node PI may be connected to a first electrode of a plurality of electrodes.

[0015] In an exemplary embodiment, the electrical stimulator may include a first digital to analog converter (DAC), a main current source, a current dependent voltage source, a second digital to analog converter (DAC), an auxiliary current source, and an adder unit. In an embodiment, the first DAC may be configured to receive a first pair of digital values for the amplitude and the frequency from the processing unit, and convert the first pair of digital values to a first pair of analog values. The main current source may be configured to generate a main electric current according to the first pair of analog values. The current dependent voltage source may be connected to the main current source through a switch S7. Switch S7 may be controlled by the processing unit. The second DAC may be configured to receive a second pair of digital values for the amplitude and the frequency from the processing unit, and convert the second pair of digital values to a second pair of analog values. The auxiliary current source may be configured to generate an auxiliary electric current according to the second pair of analog values. In an embodiment, the adder unit may include a first adder input, a second adder input, and an adder output. The first adder input may be connected to the main current source through a switch S8. Switch S8 may be controlled by the processing unit. The second adder input may be connected to the auxiliary current source through a switch S9. Switch S9 may be controlled by the processing unit. In an exemplary embodiment, the adder unit may be configured to load a sum of the first adder input and the second adder input to the adder output. The main current source may be connected to the processing unit through the first DAC and a first filter. The auxiliary current source may be connected to the processing unit through the second DAC and a second filter. An output of the current dependent voltage source may be connected to node PI through a switch S3 and a voltage/current limiter. Switch S3 and the voltage/current limiter may be controlled by the processing unit. The adder output may be connected to node PI through a switch S4 and the voltage/current limiter. Switch S4 may be controlled by the processing unit. An output of the auxiliary current source may be connected to node PI through a switch S5 and the voltage/current limiter. Switch S5 may be controlled by the processing unit.

[0016] In an embodiment, the circuit may further include a DC canceller module, an echo canceller module, a band-pass filter, a first amplifier, an anti-aliasing filter, and a first analog- to-digital converter (ADC). In an exemplary embodiment, the DC canceller module may be connected to input node PI through a buffer B2 and a switch S I. Switch SI may be controlled by the processing unit. The DC canceller module may be configured to suppress DC data of input node PI. In an embodiment, the echo canceller module may be connected to input node PI through a buffer B3 and a switch S2. Switch S2 may be controlled by the processing unit. The echo canceller module may be configured by the processing unit to suppress echoes of AC data of input node PI. In an exemplary embodiment, the band-pass filter may be connected to input node PI through a buffer B l and a switch S 10. Switch S 10 may be controlled by the processing unit. Outputs of the DC canceller module and the echo canceller module may be connected to an input node of the band-pass filter. An output of the band-pass filter may be connected to a first differential input node of the differential amplifier. The first amplifier may be configured to amplify an output of the differential amplifier. The anti-aliasing filter may be connected to the amplifier output. The first ADC may be connected to an output of the anti- aliasing filter. An output of the first ADC may be loaded to the processing unit.

[0017] In an exemplary embodiment, the processing unit may be further configured to receive voltage and current values of the first electrode from node PI through a voltage/current limiter, a switch S6, a third filter, a second amplifier, and a second analog-to-digital converter (ADC), and calculate an electrical impedance by processing the voltage and the current values of the first electrode.

[0018] In an embodiment, the processing unit may be further configured to generate a high voltage by a high-voltage generator module, and load the high voltage on node PI through a switch S 12. Switch S 12 may be controlled by the processing unit.

[0019] In an exemplary embodiment, the differential amplifier may include an instrumentation amplifier. A ground node of the instrumentation amplifier may be connected to a drive right leg (DRL) circuit.

[0020] In an embodiment, node P2 may be connected to a second electrode of the plurality of electrodes through a switch S I 1. Switch S l l may be controlled by the processing unit. The plurality of electrodes may include an electroencephalography (EEG) electrode connected to a head of a patient.

[0021] In another general aspect, the present disclosure describes a method for electrical stimulation of a brain. The method may include injecting an electric current into the brain through a first electrode of a plurality of electrodes, measuring a voltage difference between a pair of electrodes of the plurality of electrodes by a transceiver module, obtaining a an electrical impedance map of the brain by an electrical impedance tomography (EIT) imaging process, positioning a second electrode of the plurality of electrodes on the head of the patient according to the electrical impedance map, injecting an electrical signal to the second electrode by an electrical stimulator, and measuring a voltage of the second electrode by the transceiver module. The plurality of electrodes may be placed on a head of a patient. The electric current may be generated by an electrical stimulator. The transceiver module may configured to receive data from the pair of electrodes. The electric current and the voltage difference may be used as boundary values in the EIT imaging process. Injecting the electrical signal and measuring the voltage may be performed simultaneously.

[0022] Other systems, methods, features and advantages of the implementations will be, or will become, apparent to one of ordinary skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description and this summary, be within the scope of the implementations, and be protected by the claims herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawing figures depict one or more implementations in accord with the present teachings, by way of example only, not by way of limitation. In the figures, like reference numerals refer to the same or similar elements.

[0024] FIG. 1 shows a schematic of an implementation of a circuit for electrical stimulation of a brain according to one implementation of the present disclosure.

[0025] FIG. 2 shows a schematic of an implementation of a transceiver module according to one implementation of the present disclosure.

[0026] FIG. 3 shows a schematic of an implementation of an electrical stimulator according to one implementation of the present disclosure.

[0027] FIG. 4 shows a schematic of an implementation of an amplification unit according to one implementation of the present disclosure.

[0028] FIG. 5 shows a schematic of an implementation of a circuit for electrical stimulation of a brain according to one implementation of the present disclosure.

[0029] FIG. 6 shows a flowchart of an implementation of a method for electrical stimulation of a brain according to one implementation of the present disclosure.

DESCRIPTION OF EMBODIMENTS

[0030] In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be apparent that the present teachings may be practiced without such details. In other instances, well known methods, procedures, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present teachings.

[0031] The following detailed description is presented to enable a person skilled in the art to make and use the methods and devices disclosed in exemplary embodiments of the present disclosure. For purposes of explanation, specific nomenclature is set forth to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that these specific details are not required to practice the disclosed exemplary embodiments. Descriptions of specific exemplary embodiments are provided only as representative examples. Various modifications to the exemplary implementations will be readily apparent to one skilled in the art, and the general principles defined herein may be applied to other implementations and applications without departing from the scope of the present disclosure. The present disclosure is not intended to be limited to the implementations shown, but is to be accorded the widest possible scope consistent with the principles and features disclosed herein.

[0032] Herein is disclosed a novel circuit and method for electrical stimulation of a brain. The circuit includes a number of electrical stimulators that generate electric current/voltage. The electric current/voltage is injected to one or more of electrodes that are place on the head of a patient. Simultaneously, electroencephalography (EEG) signals are recorded via the same electrodes by a number of transceiver modules. The transceiver modules can also measure the electrical impedance distribution of the head by utilizing the electrical stimulators to inject electric current to the head boundaries via different pairs of electrodes placed on the head, and performing an electrical impedance tomography (EIT) imaging process by a processing unit. The impedance distribution can be used to find modified positioning of electrodes for an improved electrical stimulation of the head.

[0033] FIG. 1 shows a schematic of an implementation of a circuit 100 for electrical stimulation of a brain according to one implementation of the present disclosure. Circuit 100 may include a plurality of electrical stimulators 102, a plurality of electrodes 104, a crossbar switch 106, and a processing unit 108. Each of plurality of electrical stimulators 102 may be configured to generate an electrical signal. Crossbar switch 106 may include a plurality of individual switches 110. Processing unit 108 may be configured to provide a connection between at least one of plurality of electrical stimulators 102 and a first electrode 112 of plurality of electrodes 104 through an individual switch of plurality of individual switches 110 by turning on the individual switch.

[0034] In an embodiment, circuit 100 may further include a plurality of transceiver modules 114. Plurality of transceiver modules 114 may include a first transceiver module 116. In an exemplary embodiment, First transceiver module 116 may include an input node PI, an input node P2, and an output node Ol. Input node PI may be connected to a second electrode 118 of plurality of electrodes 104. Input node P2 may be connected to a third electrode 120 of plurality of electrodes 104. Output node Ol may be connected to processing unit 108. In an embodiment, processing unit 108 may be configured to control data transfer through plurality of transceiver modules 114. Transceiver module 116 may be configured to receive data from second electrode 118 and third electrode 120. In another embodiment, first electrode 112 may be the same as second electrode 120.

[0035] In an exemplary embodiment, circuit 100 may further include an adder module 122. Adder module 122 may be configured to receive data from an output node DRLl of first transceiver module 116 and receive data from an output node DRL2 of a second transceiver module 124 of plurality of transceiver modules 114. In an embodiment, a sum of data on output node DRLl and data on output node DRL2 may be loaded to an output node SUM of adder module 122.

[0036] FIG. 2 shows a schematic of an implementation of a transceiver module according to one implementation of the present disclosure. In an embodiment, first transceiver module 116 may further include a DC canceller module Yl, an echo canceller module Y2, a first band-pass filter Y31, a second band-pass filter Y32, a differential amplifier Y4, an amplifier Y5, an anti- aliasing filter Y6, an analog-to-digital converter (ADC) Y7, and an output node OUT. In an exemplary embodiment, DC canceller module Yl may be connected to input node PI through a buffer B2 and a switch SI. Switch SI may be controlled by processing unit 108. DC canceller module Yl may be configured to suppress DC data of input node PI. In an embodiment, echo canceller module Y2 may be connected to input node PI through a buffer B3 and a switch S2. Switch S2 may be controlled by processing unit 108. Echo canceller module Y2 may be configured to suppress echoes of AC data of input node PI. In an exemplary embodiment, first band-pass filter Y31 may be connected to input node PI through a buffer Bl and a switch S10. Switch S10 may be controlled by processing unit 108. Outputs of DC canceller module Yl and echo canceller module Y2 may be connected to an input node of first band-pass filter. In an embodiment, second band -pass filter Y32 may be connected to input node P2 through a switch Sll. Switch Sll may be controlled by processing unit Y32. In an exemplary embodiment, differential amplifier Y4 may include a first differential input node 202, a second differential input node 204, a differential output node 206, and a differential ground node DRL. In an embodiment, the differential input node 202 may be connected to an output of first band -pass filter Y31. Second differential input node 204 may be connected to an output of second bandpass filter Y32. Differential ground node DRL may be connected to an output node DRLl. In an exemplary embodiment, differential amplifier Y4 may be configured to load an amplification of a difference between data on first differential input node 202 and data on second differential input node 204 to differential output node 206. In an embodiment, amplifier Y5 may be configured to amplify data of differential output node 206. Anti-aliasing filter Y6 may be connected to amplifier Y5 output. ADC Y7 may be connected to an output of anti- aliasing filter Y6. Output node OUT may be connected to an output of ADC Y7.

[0037] FIG. 3 shows a schematic of an implementation of an electrical stimulator 300 of plurality of electrical stimulators 102 according to one implementation of the present disclosure. In an exemplary embodiment, electrical stimulator 300 may include a power supply 302, a digital to analog converter (DAC) 304, a current source 306, a voltage source 308, a node XI, and a node X2. In an embodiment, DAC 304 may be configured to generate an amplitude and a frequency of the electrical signal. Current source 306 may be connected to an output node of DAC 304. The voltage source 308 may be connected to the output node of DAC 304. Node XI may be connected to current source 306 through a voltage/current limiter 310 and a switch SB1, and may be connected to voltage source 308 through voltage/current limiter 310 and a switch SB2. In an exemplary embodiment, voltage/current limiter 310 and switches SB1 and SB2 may be controlled by processing unit 108. Node X2 may be connected to power supply 302.

[0038] In an embodiment, processing unit 108 may be configured to provide a digital amplitude and a digital frequency of the electrical signal to DAC 304. In an exemplary embodiment, power supply 302 may include an isolated DC power supply.

[0039] In an exemplary embodiment, the electrical stimulator may further include a digital data isolator 312. Digital data isolator 312 may be configured by processing unit 108 to provide a digital amplitude and a digital frequency of the electrical signal to DAC 304.

[0040] FIG. 4 shows a schematic of an implementation of an amplification unit according to one implementation of the present disclosure. Referring to FIGS. 1 and 4, in an embodiment, the circuit may further include an amplification module 400. Amplification module 400 may include a filter 402, an amplifier 404, and analog to digital converter (ADC) 406. In an exemplary embodiment, filter 402, amplifier 404, and ADC 406 may be connected in series. Amplification module 400 may be configured to provide a path between first electrode 112 or second electrode 118 and an input of processing unit 108.

[0041] In an exemplary embodiment, processing unit 108 may be further configured to calculate an electrical impedance by measuring voltage and current values of first electrode 112 or second electrode 118 through the amplification module. In an embodiment, plurality of electrodes 104 may include an electroencephalography (EEG) electrode connected to a head of a patient.

[0042] FIG. 5 shows a schematic of an implementation of a circuit 500 for electrical stimulation of a brain according to one implementation of the present disclosure. In an embodiment, the circuit 500 may include a differential amplifier Y4, an electrical stimulator 502, and a processing unit Y8. In an embodiment, differential amplifier Y4 may be configured to amplify a difference between data on a node PI and a node P2. Electrical stimulator 502 may be configured to load an electrical signal on node PI. Processing unit Y8 may be configured to generate an amplitude and a frequency of the electrical signal. Referring to FIG. 1, in an exemplary embodiment, node PI may be connected to second electrode 118.

[0043] In an exemplary embodiment, electrical stimulator 502 may include a first digital to analog converter (DAC) Y9, a main current source Y14, a current dependent voltage source Y16, a second digital to analog converter (DAC) Y10, an auxiliary current source Y15, and an adder unit Y20. In an embodiment, first DAC Y9 may be configured to receive a first pair of digital values for the amplitude and the frequency from processing unit Y8, and convert the first pair of digital values to a first pair of analog values. Main current source Y14 may be configured to generate a main electric current according to the first pair of analog values. Current dependent voltage source Y16 may be connected to the main current source through a switch S7. Switch S7 may be controlled by processing unit Y8. Second DAC Y10 may be configured to receive a second pair of digital values for the amplitude and the frequency from processing unit Y8, and convert the second pair of digital values to a second pair of analog values. Auxiliary current source Y15 may be configured to generate an auxiliary electric current according to the second pair of analog values. In an embodiment, Adder unit Y20 may include a first adder input, a second adder input, and an adder output. The first adder input may be connected to main current source Y14 through a switch S8. Switch S8 may be controlled by processing unit Y8. The second adder input may be connected to auxiliary current source Y15 through a switch S9. Switch S9 may be controlled by processing unit Y8. In an exemplary embodiment, adder unit Y20 may be configured to load a sum of the first adder input and the second adder input to the adder output. Main current source Y14 may be connected to processing unit Y8 through first DAC Y9 and a first filter Yll. Auxiliary current source Y15 may be connected to processing unit Y8 through second DAC Y10 and a second filter Y12. An output of current dependent voltage source Y16 may be connected to node PI through a switch S3 and a voltage/current limiter Y21. Switch S3 and voltage/current limiter Y21 may be controlled by processing unit Y8. The adder output may be connected to node PI through a switch S4 and voltage/current limiter Y21. Switch S4 may be controlled by processing unit Y8. An output of auxiliary current source Y15 may be connected to node PI through a switch S5 and the voltage/current limiter Y21. Switch S5 may be controlled by processing unit Y8.

[0044] In an embodiment, circuit 500 may further include a DC canceller module Yl, an echo canceller module Y2, a first band-pass filter Y31, a second band-pass filter Y32, a first amplifier Y5, an anti-aliasing filter Y6, and a first analog-to-digital converter (ADC) Y7. In an exemplary embodiment, DC canceller module Yl may be connected to input node PI through a buffer B2 and a switch SI. Switch SI may be controlled by processing unit Y8. DC canceller module Yl may be configured to suppress DC data of input node PI. In an embodiment, echo canceller module Y2 may be connected to input node PI through a buffer B3 and a switch S2. Switch S2 may be controlled by the processing unit. Echo canceller module may be configured by processing unit Y8 to suppress echoes of AC data of input node PI. In an exemplary embodiment, first band-pass filter Y31 may be connected to input node PI through a buffer Bl and a switch S10. Switch S10 may be controlled by processing unit Y8. Outputs of DC canceller module Yl and echo canceller module Y2 may be connected to an input node of first band-pass filter Y31. An output of first band-pass filter Y31 may be connected to a first differential input node of the differential amplifier. Second band-pass filter Y32 may be connected to input node P2 through a switch Sll. Switch Sll may be controlled by processing unit Y8. An output of second band -pass filter Y32 may be connected to a first differential input node of differential amplifier First amplifier Y5 may be configured to amplify an output of the differential amplifier Y4. Anti-aliasing filter Y6 may be connected to the amplifier output. First ADC Y7 may be connected to an output of anti-aliasing filter Y6. An output of first ADC Y7 may be loaded to processing unit Y8.

[0045] In an exemplary embodiment, processing unit Y8 may be further configured to receive voltage and current values of second electrode 118 from node PI through voltage/current limiter Y21, a switch S6, a third filter Y17, a second amplifier Y18, and a second analog-to- digital converter (ADC) Y19, and calculate an electrical impedance by processing the voltage and the current values of second electrode 118. [0046] In an embodiment, processing unit Y8 may be further configured to generate a high voltage by a high- voltage generator module Y13, and load the high voltage on node PI through a switch S12. Switch S12 may be controlled by the processing unit.

[0047] In an exemplary embodiment, differential amplifier Y4 may include an instrumentation amplifier. A ground node of the instrumentation amplifier may be connected to a drive right leg (DRL) circuit.

[0048] Referring again to FIG. 1, in an embodiment, node P2 may be connected to third electrode 120 of plurality of electrodes 104 through a switch Sll. Switch Sll may be controlled by processing unit Y8.

[0049] FIG. 6 shows a flowchart of an implementation of a method 600 for electrical stimulation of a brain according to one implementation of the present disclosure. Method 600 may include injecting an electric current into the brain through a first electrode of a plurality of electrodes (step 602), measuring a voltage difference between a pair of electrodes of the plurality of electrodes by a transceiver module (step 604), obtaining a an electrical impedance map of the brain by an electrical impedance tomography (EIT) imaging process (step 606), positioning a second electrode of the plurality of electrodes on the head of the patient according to the electrical impedance map (step 608), injecting an electrical signal to the second electrode by an electrical stimulator (step 610), and measuring a voltage of the second electrode by the transceiver module (step 612). The plurality of electrodes may be placed on a head of a patient. The electric current may be generated by an electrical stimulator. The transceiver module may be configured to receive data from the pair of electrodes. The electric current and the voltage difference may be used as boundary values in the EIT imaging process. Injecting the electrical signal and measuring the voltage may be performed simultaneously.

Example 1: Multi-isle HD tDCS/tACS/tRNS (using isolated currents sources)

[0050] This example introduces a High Definition current stimulation system which can be implemented by using electrical stimulators that include two or more common electrodes as a sink or a source on different sets of electrodes. In this example, one side of two or more sets of electrodes are connected to two or more sink/source electrodes (through a crossbar switch) and all other sides of the selected isolated current sources are connected to the desired electrodes. Table 1 shows switch states for the circuit of Example 1 according to FIGS. 1-5.

Table 1. Switch states for the circuit of Example 1 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S1 1 S12 SB1 SB2

0 0 0 0 0 0 0 0 0 0 0 0 1 0

Example 2: EEG recording

[0051] This Example shows how to use the system as a signal recorder (EEG) without stimulations. Table 2 shows switch states for the circuit of Example 2 according to FIGS. 1-

Table 2. Switch states for the circuit of Example 2

Example 3: EIT imaging

[0052] This example introduces an electrical impedance tomography system. Table 3 shows switch states for the circuit of Example 3 according to FIGS. 1-5.

Table 3. Switch states for the circuit of Example 3 [0053] While the foregoing has described what are considered to be the best mode and/or other examples, it is understood that various modifications may be made therein and that the subject matter disclosed herein may be implemented in various forms and examples, and that the teachings may be applied in numerous applications, only some of which have been described herein. It is intended by the following claims to claim any and all applications, modifications and variations that fall within the true scope of the present teachings.

[0054] Unless otherwise stated, all measurements, values, ratings, positions, magnitudes, sizes, and other specifications that are set forth in this specification, including in the claims that follow, are approximate, not exact. They are intended to have a reasonable range that is consistent with the functions to which they relate and with what is customary in the art to which they pertain.

[0055] The scope of protection is limited solely by the claims that now follow. That scope is intended and should be interpreted to be as broad as is consistent with the ordinary meaning of the language that is used in the claims when interpreted in light of this specification and the prosecution history that follows and to encompass all structural and functional equivalents. Notwithstanding, none of the claims are intended to embrace subject matter that fails to satisfy the requirement of Sections 101, 102, or 103 of the Patent Act, nor should they be interpreted in such a way. Any unintended embracement of such subject matter is hereby disclaimed.

[0056] Except as stated immediately above, nothing that has been stated or illustrated is intended or should be interpreted to cause a dedication of any component, step, feature, object, benefit, advantage, or equivalent to the public, regardless of whether it is or is not recited in the claims.

[0057] It will be understood that the terms and expressions used herein have the ordinary meaning as is accorded to such terms and expressions with respect to their corresponding respective areas of inquiry and study except where specific meanings have otherwise been set forth herein. Relational terms such as first and second and the like may be used solely to distinguish one entity or action from another without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "a" or "an" does not, without further constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0058] The Abstract of the Disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in various implementations. This is for purposes of streamlining the disclosure, and is not to be interpreted as reflecting an intention that the claimed implementations require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed implementation. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separately claimed subject matter.

[0059] While various implementations have been described, the description is intended to be exemplary, rather than limiting and it will be apparent to those of ordinary skill in the art that many more implementations and implementations are possible that are within the scope of the implementations. Although many possible combinations of features are shown in the accompanying figures and discussed in this detailed description, many other combinations of the disclosed features are possible. Any feature of any implementation may be used in combination with or substituted for any other feature or element in any other implementation unless specifically restricted. Therefore, it will be understood that any of the features shown and/or discussed in the present disclosure may be implemented together in any suitable combination. Accordingly, the implementations are not to be restricted except in light of the attached claims and their equivalents. Also, various modifications and changes may be made within the scope of the attached claims.