The present patent application relates to time-resolved (TR) or time-gated (TG) diffuse optic tomography (DOT) imaging modality. Biomedical DOT imaging systems are macroscopic medical imaging devices that use laser photons, which penetrate inside the imaging tissue from the source position. The laser photons are acquired at the PN type semiconductor photodetectors as photocurrents. Photocurrents are converted into electrical voltages by electronic analog integrator circuits, and then converted into digital values by analog-to-digital converters (ADCs) . DOT modality uses digital voltage values in the mathematical image reconstruction algorithms and reconstructs the hidden sub-tissue images. Electronic circuits are employed to convert the input photodiode currents into output voltage values. Accordingly, these electronic circuits are converting electric currents that are generated in PIN semiconductor photodiodes flowing through p-type (majority current carriers are holes), n-type (majority current carriers are electrons), and pn-junctions (weak inversion region - majority and minority current carriers) .

The two big companies Burr-Brown and Texas Instruments (TI) are manufacturing most famous analog current input digital voltage output DDC series analog-to-digital converters (ADC) used for medical imaging purposes. Some DDC series analog current input digital voltage output ADCs are capable to integrate and convert 2, 4, 8, 16, 32, and 64 analog current inputs. These are DDC112,

DDC114, DDC118, DDC232, and DDC364 series, respectively.

The following patents also relate to the prior art in this research field. US Patent No. 5841310 and patent publication "Current-to- voltage integrator for analog-to-digital converter, and method". US patent No. 5515260 "Current-voltage conversion circuit, current compressing and extension circuit, automatic exposure control system, and automatic exposure control system with built-in sensor". WO World patent "Current-to-voltage integrator for ADC". US patent No. "Current-to-voltage integrator for analog-to-digital converter, and method". European patent EP No. "Current-to-voltage integrator for ADC". US patent No. US5103230A "Precision digitized current integration and measurement circuit". US patent No. US5703589A "Switched capacitor input sampling circuit and method for delta sigma modulator".

In the above-mentioned DDC series analog current input digital voltage output integrator with ADC circuit manuals, it was not mentioned about current switching methodology. It was stated that the switching of input current comes from the control & command circuit; however, there is no detailed information on how the current at the input is switched. In that technique, it was stated that the current / voltage ADC cycle is at least 330 microseconds (□s) . On the other hand, there has been no study on reducing the integration times. Only time diagrams are available for this subject. The voltage pulses come from the pulse generator circuit. Pulse generation and sending them to the analog circuit block according to a specific synchronization can be made by digital control & command timing circuits. Microcontroller must be embedded in the digital block, controlling both timings and generating the square pulse signals. The prior art does not refer to the producing of timings.

In the prior art, the phase timing delays of transistors, which will perform the integrator switching with the high-resolution special digital-to-time converter (DTC) circuits, can be provided. But in this case, complexity of the circuit and the switched capacitor noises will raise. In order to eliminate these negative feedbacks, active electronic filter circuits must be designed and used .

Ultra-short square pulses used in DTC circuits are described in the article "High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging" IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015. By using the method in this study, it is possible to design and carry out switching circuits that can accomplish integration processes in 100 femtoseconds. But even in order to make only timing circuit, the complex integrated circuits (ICs) must be designed and implemented such as low noise buffer (LNB) , ramp generator, digital to analog converter (DAC) , phased- lock loop (PLL) circuits. Above-mentioned article for making DTC circuit might be used as a reference. CMOS transistors would be employed as switches and driven by the DTC timing command & control circuitry so that the photodiode current can be switched by the corresponding timing signals generated in the DTC timing circuit. But in this case, both the complexity of the complete circuitry, electrical noises and other photonic artefacts will raise. As it is clearly explained in the above-mentioned paragraph, the digital control & command signals, which turn ON and OFF integrator switches, are generated in DTC circuit block according to a very large-scale integration (VLSI) circuit technology concept. To summarize, it is necessary to design digital timing circuit blocks, analyze and implement the IC. Electrical integrity between blocks should be provided. As mentioned above, the design of these circuit blocks and their placements in the IC circuitry also bring enormous burdens. They require structurally increased complexity of the circuit, resulting in increasing the electrical noises in the circuit. In addition, in order to prevent these increased electrical noises, it is necessary to design and implement the electrical active filters. The greatest portion of electrical noises is related to the transistor switching of the integrator and input photodiode.

As a result, timing circuits in the state of art are very expensive. Therefore, the need for a new method in the present technique has gradually increased.

BRIEF DESCRIPTION OF THE INVENTION

It is an object of the present invention to enable the separation of different tissue types in diffuse optical tomography (DOT) modality, which is one of the biomedical optical imaging methods.

It is a further object of the present invention to reduce the current / voltage integration timings of the analog current-to- voltage integrator with ADC converter circuits to far below the existing values.

It is another object of the present invention to eliminate the complex digital control & command circuits similar to DTC in analog current input digital voltage output integrator with ADC converter ICs .

Novelty of the invention can be disclosed as follows. Time delays between metal wires will be responsible for the integration processes as done in programmable delay chips (PDCs) . Integrating CMOS switch transistors will have a phase delay while the trigger pulse drives them.

For example, the 20-micrometer metal or polysilicon line length difference causes approximately 100 femtoseconds time delay. The length difference of 1 micrometer results in a time delay of approximately 5 femtoseconds. Desired time delays will be obtained by triggering the gate node of CMOS switch transistors with pulse voltage that will be driven from the microcontroller control & command circuitry, which are responsible for the integration process on the circuit. Length differences will be made in the layout process of circuit.

REFERENCE NUMBERS

10 Tissue

20 Source position 30 Detector position 40 Transmission delay line circuit 50 Switching Circuit 60 Normally Open (NO) switch

70 Normally Close (NO) switch

80 Integrator circuitry

90 Operational Amplifier (Op-Amp) Integrated Circuit (IC)

100 Differential Amplifier Circuit

110 Current Source

BRIEF DESCRIPTION OF THE FIGURES Figure 1 shows function of the photon trajectory between source and detector positions.

Figure 2 shows source and detector signals of the time-resolved diffuse optical tomography (TRDOT) system.

Figure 3 shows transmission delay line circuit and switches.

Figure 4 shows integrator switches .

Figure 5 illustrates integrator circuit schematic.

Figure 6 shows internal structure of the operational amplifier

(Op-Amp) at the transistor level.

Figure 7 shows a circuit diagram of the operational amplifier

(Op-Amp) with low-pass filters.

DETAILED DESCRIPTION OF THE INVENTION In this detailed description, the invention is explained by examples, which will not have any limiting effect on a better understanding of the subject.

Accordingly, the present invention provides electronic pulse generator and driver circuit for laser source of diffuse optical tomography (DOT) systems, which is part of the biomedical optical imaging modality used for the differentiation of tissue types. The integrated circuit (IC), which is intended to be used in electronic data acquisition unit of DOT systems, have capability to integrate in femtosecond (fs) timing ranges.

Transmission delay line circuit (TDLC) , which has one-micrometer difference between two lines, will enable to realize the approximately five femtoseconds integration time. One-micrometer transmission line is hundred times bigger than today's ten- nanometer channel length technology. One-micrometer transmission line and even longer layout would be made inside the chip, easily. It could be even made smaller transmission lines. Thus, it is possible to integrate photodiode currents in femtoseconds (fs) .

Figure 1 shows the photons that are collected at detector location (30) sent from the source position (20) into the tissue (10) from the surface. Depending on the optical properties of the tissue (D _a absorption and D _s scattering coefficients), the measured light intensity photo current values in the photodiode at the detector location will vary for different integration times. Depend on the tissue type; the measured light intensity value differ at the same integration time for different tissue types. By measuring the photodiode currents for different tissue types, the characteristics of the tissue types can be formulated.

A large number of small integration time measurements will give an idea of the tissue type, and on the contrary, the measurements made in the larger integration times will not provide detailed information .

In the case, where the laser photons are sent as one-picosecond voltage pulse width from a source position (20) in the time domain as shown in Figure 2, the physical appearance of the voltage signal acquired in the detector location (30) is a sudden spark and then exponentially decaying signal as shown in Figure 2. The frontier photons, which are collected at the detector location, produces sudden peak voltage, then the photons coming from deeper layers generate the exponentially degrading voltage signal, consequently much deeper photons arrive later.

These systems are known as time-resolved diffuse optical tomography (TRDOT) or time-gated diffuse optic tomography (TGDOT) systems in the literature. TRDOT devices are expensive systems to build. It does require photo multiplying tubes (PMTs), optical mirrors, polarizers, lenses, optical tables, etc., which are sensitive to single photon and laboratory conditions such as dark rooms .

In the present invention, the electronic circuit is provided to ensure that the same process performed by expensive TRDOT systems is carried out within the single chip. Accordingly, switching of the input photodiode current can be performed in ultra-short times, and as a result, TRDOT data acquisition process is accomplished quickly. Thus, photons generated by ultra-short square voltage pulse sent from the laser source position on tissue surface will be able to draw an exponentially decaying photo-voltage graph at the detector side. The new microelectronic integrator circuit (IC) would measure it, which is sufficiently fast to generate exponentially degrading voltage at the detector side. Thus, exponentially decaying time-resolved voltage signal would be measured in the detector position by ultrafast switching the input photodiode current.

Ultrafast switching of input photodiode current is nearly independent on the technology to be used and the time delay circuit will be designed with different length metal or polysilicon lines.

Operating principle of the designed circuit is described in Figures 3 and 4. In the most general sense, the integration operation carried out by the integrator circuitry (80) provided at the circuit output is performed by means of the fact that a transmission delay line circuit (40) activates and de-activates switching circuits (50) . The transmission delay line circuit (40) is comprised of a switching circuit (50) and LI and L2 metal lines. While switching circuit (50) generates a triggering pulse voltage to be used for activating and de-activating switches, LI and L2 transmission lines form time differences to be occurred due to length differences of LI and L2 transmission lines. Due to length differences of LI and L2 metal lines, once voltage pulse reaches the Normally Open (NO) switch (60) at the end of LI line in Figure 2 and switches OFF its circuit, the pulse signal does not reach the end of L2 yet. Therefore, the Normally Closed (NO) switch (70) maintains its closed state. Integration process is carried out until the moment that the pulse input, which is occurred due to transmission delay line and is to reach the end of L2, switches ON the NO switch (70) . Afterwards, pulse input switches ON the NO switch (70) circuit and Integration process is completed.

In Figure 5, the electronic circuit is shown which comprises of n- channel and p-channel MOSFET transistors, integration capacity (Cint) and an operational amplifier (Op-Amp) (90) . In Figure 6, there are six MOSFETs (2 p-channel MOSFET and 4 n-channel MOSFET transistors) and one passive resistor in the Op-Amp (90) . The Op- Amp (90) forms the core of the analog integrator circuit and has a differential amplifier circuit (100) at its center. The differential amplifier circuit (100) consists of four transistors (M7, M8 , M9, and M10) . M7 , M8 , M9, M10 MOSFET transistors are part of the differential amplifier (100) which amplifies the small voltage signal differences in the input and transfers it to the output. Mil and M12 n-channel MOSFETs are connected to the current source of the differential amplifier (110) with the current mirror. N-channel MOSFET transistors' bulks are at the lowest voltage level which is ground; p-channel MOSFET transistors bulks are connected to the highest voltage level which is VDD (1 Volt DC) .

Ml transistor provides the 1 Volt DC (VDC) voltage required by the circuit shown in Figure 5. Ml p-channel MOSFET transistor supplies the 1 VDC Vref reference voltage to the circuit. The <JVref voltage pulse is supplying the trigger signal to the Ml transistor switch' s gate node. The source node of the p-channel Ml transistor is connected to the <JVref port. The ref pulse voltage is connected to the gate input. When the logic 1 changes to logic 0, Ml transistor turns ON and closes the circuit, which is normally open (NO) at the beginning. In this way, the 1 VDC Vref reference voltage connected to the source node of the Ml transistor is supplied to the (+) end of the Cint (30) integration capacitance as shown in Figure 5. Waitl and Wait2 pulse signals are driving the gate nodes of the M6 and M5 p-channel MOSFET transistors. When the M2 p- channel transistor turns ON, Cint integrating capacitance is charging voltage across current flow path through Ml, M5, and M2 MOSFET transistors.

The charging process of Cint integration capacitance can be summarized as follows. The normally open (NO) Ml transistor is saturated and turn ON, the NO M6 transistor continues to be NO, and the ( + ) end of the Cint integrating capacitance reaches positive 1-VDC Vref voltage. At the same time, the NO M5 p-channel MOSFET transistor is switched ON, the NO M2 transistor is switched ON and the (-) node voltage of Cint integrating capacitance falls to the ground level. Immediately after that time, the M6 transistor which has been already NO continues to be NO; the M5 transistor, which is closed in the previous step, opens; in this case, both the ( + ) and (-) terminals of the Cint capacitance turns to the open circuit position. At this time, the Cint capacitance sets to the 1-VDC reference voltage and keeps its value. In the next step, the M5 transistor closes for the integration process, the NO n-channel M4 transistor' s FINT2 gate node is triggered by driving high logic Ί' level, hence it turns ON. The M3 weak inversion mode reverse connected NO M3 transistor is driven once the FINT1 triggering -1 VDC voltage signal arrive the gate node of the M3 transistor and it turns OFF. Thus, it turns to open- circuit, and the integration process is terminated immediately after signal arrives at this node.

Switching transistors, integration capacitance and low pass RC filters to eliminate the switching noises placed on the gate inputs of the switches can be seen in Figure 7.