Electronic circuit

The present invention relates to an electronic circuit as well as an electronic device.

The gate-source, gate-drain or drain-source voltages for NMOS and PMOS transistors in conventional CMOS circuits are typically equal to the supply voltage. However, in advanced processes like the 65nm technology, input/output IO devices are able to receive up to 2,75 V, i.e. 2,5 V nominal, across the gate-source, the gate-drain or the drain-source, while still being reliable and avoiding hot carrier degradation or oxide breakdown. On the other hand, many signaling standards like USB operate at 3,3 V. Therefore, the circuit techniques are required which are able to cope with 3.3V signaling while still using 2.5V devices.

Fig. 1 shows a circuit diagram of a conventional CMOS inverter. The inverter comprises a PMOS transistor Ml and a NMOS transistor M2 which are coupled between the supply voltage VDD and VSS. The steady state output V _OUT and the steady state input V _IN voltages will correspond to a logic high or logic low state. In both of these cases, the gate- source, the gate-drain or drain- source voltages of the transistors Ml, M2 are equal to VDD or O V according to the actual logic state of the inverter. However, as mentioned above, if the inverter is operated at 3,3 V while being fabricated using 2,5 V devices, both of the transistors Ml, M2 will experience a stress which may influence the long term reliability due to hot carrier degradation or gate-oxide breakdown. Fig. 2 shows a circuit diagram of an inverter according to the prior art. In particular, Fig. 2 relates to US 6,377,075. The circuit comprises two PMOS transistors M2, M4 and two NMOS transistors Ml, M3. The four transistors Ml - M4 are coupled in series between the supply voltage VDD and VSS. By cascoding the transistors Ml - M4, the high voltage stress as experienced by the particular devices may be reduced. The gates of the transistors are coupled to a fixed intermediate voltage ngate and pgate. The circuit according to Fig. 2 requires the provision of additional supply voltages pgate and ngate or alternatively the provision of a reference generator. However, the provision of an additional supply voltage or the provision of a reference generator will introduce an increased static current consumption.

It is therefore an object of the invention to provide an electronic circuit based on CMOS circuits, which can improve the ability of the circuit to withstand stress on the circuits due to an increased input voltage.

This object is solved by an electronic circuit according to claim 1 and an electronic device according to claim 8.

Therefore, an electronic circuit is provided comprising an input for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage and a voltage. The third transistor is coupled between the voltage and a first node. The second transistor is coupled between a second node and the output. The third transistor is coupled between the first node and the output. The fourth transistor is coupled between the supply voltage and the second node. A first reference voltage generating unit receives the voltage at the first node and the voltage as input, and its output is coupled to the gate of the second transistor. A second reference voltage generating unit receives the supply voltage and the voltage of the second node as input, and its output is coupled to the gate of the third transistor. The first and second reference voltage generating units generate a reference voltage according to at least one of the logic states of the first, second, third or fourth transistor.

As the reference voltages are generated according to the logic states of some of the transistors the generation is performed dynamically and any static currents due to static or constant reference voltage generators are avoided.

According to an aspect of the invention, the first reference voltage generating unit is implemented as a ninth transistor coupled between the first node and the gate of the second transistor and the second reference voltage generating unit is implemented as a seventh transistor coupled between the second node and the gate of the third transistor. The gate of the seventh transistor is coupled to the supply voltage, and the gate of the ninth transistor is coupled to the voltage. The implementation of the reference voltage generating units as transistors is advantageous regarding the costs, the required chip area and the static current requirements.

According to a further aspect of the invention, the first and third transistors are of a first conductivity type, while the second and fourth transistors are of a second conductivity type.

According to an aspect of the invention, the circuit comprises a fifth transistor coupled between input and the gate of the first transistor and a sixth transistor coupled between the input and the gate of the fourth transistor. A third reference voltage generating

unit receiving the supply voltage and the voltage at a third node as input, and its output is coupled to the gate of the fifth transistor. A fourth reference voltage generating unit receives the voltage and the voltage at a fourth node as input signals, and its output is coupled to the gate of the sixth transistor. The third and fourth reference voltage generating units generate a reference voltage according to the logic states at the gate of the fourth transistor and the gate of first transistor, respectively.

According to an aspect of the invention, the third reference voltage generating unit is implemented as an eighth transistor coupled between the gate of the fourth and fifth transistor and the fourth reference voltage generating unit is implemented as a tenth transistor coupled between a fourth node and the gate of the sixth transistor. The gate of the eighth transistor is coupled to the supply voltage, wherein the gate of the tenth transistor is coupled to the voltage.

According to a further aspect of the invention an eleventh transistor coupled between the fourth node and the gate of the third transistor, a twelfth transistor coupled between the gates of the first and second transistor, a thirteenth transistor coupled between the first node and the gate of the sixth transistor, and a fourteenth transistor coupled between the second node and the gate of the fifth transistor. The gates of the eleventh and the fourteenth transistor are coupled to the supply voltage. The gates of the twelfth and thirteenth transistor are coupled together and are coupled to the voltage Vss. The eleventh, twelfth, thirteenth and fourteenth transistor are provided to avoid sub-threshold currents in the seventh, eighth, ninth and tenth transistors by providing high resistors in form of the turned off transistors.

The invention also relates to an electronic device comprising an input for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage and a voltage. The third transistor is coupled between the voltage and a first node. The second transistor is coupled between a second node and the output. The third transistor is coupled between the first node and the output. The fourth transistor is coupled between the supply voltage and the second node. A first reference voltage generating unit receives the voltage at the first node and the voltage as input, and its output is coupled to the gate of the second transistor. A second reference voltage generating unit receives the supply voltage and the voltage of the second node as input, and its output is coupled to the gate of the third transistor. The first and second reference voltage generating units generate a reference voltage according to at least one of the logic states of the first, second, third or fourth transistor.

The invention relates to the idea to avoid constant reference voltages and to rather introduce dynamically generated reference voltages depending on the actual logic state of the circuit. Accordingly, additional supply rails or bias generating circuits which may consume additional static current can be avoided.

The embodiments and advantages of the invention will now be described in detail with reference to the drawings.

Fig. 1 shows a circuit diagram of a CMOS inverter according to the prior art, Fig. 2 shows a circuit diagram of a further inverter based on CMOS circuits according to the prior art,

Fig. 3 shows a circuit diagram of an inverter according to a first embodiment, Fig. 4 shows a circuit diagram of an inverter according to a second embodiment, Fig. 5 shows a circuit diagram of an inverter according to a third embodiment,

Fig. 6 shows a graph of a transfer function of an inverter, Fig. 7 shows a graph of a transfer function of an inverter, Fig. 8 shows a graph of input, output and intermediate signals of an inverter, Fig. 9 shows a further graph of a transient function of the input, the output and intermediate signals, and

Fig. 10 shows a circuit diagram of a level shifter circuit according to a fourth embodiment.

Fig. 3 shows a circuit diagram of an inverter according to a first embodiment.

The inverter comprises a cascoded structure of four transistors, namely the NMOS transistors Ml, M3 and the PMOS transistors M2, M4. These four transistors Ml - M4 are coupled between the supply voltage VDD and VSS. The gate of the first transistor Ml is coupled to a node tgn and the gate of the fourth transistor M4 is coupled to a node tgp. The first transistor Ml is coupled between the node tn and VSS. The third transistor M3 is coupled between the output V _OUT and the node tn. The gate of the third transistor M3 is coupled to node D. The second transistor M2 is coupled between the output V _OUT and the node tp. The gate of the second transistor M2 is coupled to node C. The fourth transistor M4 is coupled between the node tp and the supply voltage VDD. The fifth transistor M5 is coupled between the node tgn

and the input V _IN and its gate is coupled to node A. A sixth transistor M6 is coupled between tgp and the input V _IN . Its gate is coupled to node B.

The inverter furthermore comprises four reference voltage generating units RA - RD. The first reference voltage generating unit RA receives the supply voltage VDD and the node tgp as inputs and its outputs corresponds to node A, i.e. its output is coupled to the gate of the fifth transistor M5. The second reference voltage generating unit RB receives VSS and the voltage at the node tgn as inputs and output is used at node B, i.e. its output is coupled to the gate of the sixth transistor M6. The third reference voltage generating unit RC receives the voltage VSS and the voltage at the node tn and its output is coupled to the gate of the second transistor M2, i.e. node C. The fourth reference voltage generating unit RN receives the supply voltage VDD and the voltage at the node tp as inputs and its output is coupled to the gate of the third transistor M3, i.e. to node D. In other words, the gate voltage of the third transistor M3 is derived from the voltage at node tp and the supply voltage VDD. The gate voltage of the second transistor M2 is derived from the voltage at node tn and VSS. Accordingly, the reference voltages can be generated dynamically without any static current. Therefore, no additional static reference voltage generating units are required such that the required static power can be reduce.

Fig. 4 shows a circuit diagram of an inverter according to the second embodiment. The circuit diagram according to the second embodiment substantially corresponds to the circuit diagram according to the first embodiment. The only difference is that the reference voltage generating units RA - RD are implemented as transistors M7- MlO, wherein the seventh and eighth transistor M7 and M8 are NMOS transistors, while the ninth and tenth transistor M9 and MlO are PMOS transistors.

It should be noted that for simplicity reasons the substrate connections of the devices are not explicitly depicted. All of the PMOS substrates are connected to VDD and all of the NMOS substrates are connected to VSS. The gate of the seventh transistor M7 is coupled to VDD, its source is coupled to the node tp and its drain is coupled to the gate of the third transistor M3. The gate of the eighth transistor M8 is coupled to the supply voltage VDD, its source is coupled to the node tgp and its drain is coupled to the gate of the fifth transistor M5. The gate of the ninth transistor M9 is coupled to VSS and its drain is coupled to the node tn while its source is coupled to the gate of the second transistor M2. The gate of the tenth transistor MlO is connected to VSS and its source is connected to tgn while its drain is connected to the gate of the sixth transistor M6.

When the input signal V _IN is high, i.e. VDD, the input signal is passed to the node tgp via the transistor M6 and the fourth transistor M4 is turned off. As the gate of the eighth transistor M8 is connected to VDD, the node A will rise to a voltage corresponding to VDD minus V _t such that the fifth transistor M5 is turned on. The node tgn will rise to a voltage corresponding to ((VDD - Vt) - V _t = VDD - 2Vt). Accordingly, the first transistor Ml is turned on and the node B rises to the voltage at the node tgn. VDD - 2V _t via the tenth transistor MlO.

The first transistor Ml keeps the node tn to the voltage VSS. Accordingly, the third transistor M3 will be turned on and hold the output voltage V _OUT to VSS such that a low output stage is present. The node C will discharge through the ninth transistor M9 to V _t above the VSS. The ninth transistor will turn off as soon as the voltage at the node C has reached the value of V _t above VSS. Accordingly, the node tp will discharge to V _t above the node C (2 Vt). As soon as the node tp has discharged to 2 Vt, the second transistor M2 will turn off and will keep the node tp at a voltage of 2 V _t . The seventh transistor M7 turns on and will connect the node D to the node tp.

In the following it will be shown that the circuit according to Fig. 4 ensures that any stress over the transistors will be within the tolerance limits. For the case of a 3 V3 signaling, the highest supply voltage is may be considered as 3,6 volt including a 10% tolerance. The threshold voltages V _t of NMOS and PMOS devices typically equal to 0,45 volt and -0,45 volt. Based on these voltages, the voltages at the different nodes are shown in the following Table 1 :

Table 1 :

Accordingly, the maximum voltages for a worst case scenario across the terminals of all of the transistors are shown below in Table 2:

Table 2:

It should be noted that all of these voltages lie within tolerance limit of 2,75 V of the transistors. All of the threshold voltages, which are used to reduce the applied voltages, are back biased (body effect). Accordingly, the threshold voltage V _t increased and will reduce the applied voltage. In addition it should be noted that no static current is present in this stable logic state. It should be noted that the above numbers in Table 1 and Table 2 have merely been chosen to describe the basic principles of the invention. The actual values should not be considered as restricting the principles of the invention.

If the input voltage V _IN switches to low (0 V), the state is passed to the node tgn via the fifth transistor M5. Accordingly, the first transistor Ml is turned off. As the gates of the tenth transistor MlO is connected to VSS, the voltages at the node B will discharge to threshold voltage V _t above VSS such that the sixth transistor M6 is turned on. The voltage at the node tgp will discharge to the threshold voltage V _t above the voltage at the node B, turning on the fourth transistor M4. The voltage at node A will discharge to the voltage at the

node tgp via the eighth transistor M8. The fourth transistor M4 will pull the voltage of the node tp to the supply voltage. This will turn on the second transistor M2 and will pull the output voltage-Vouτ to the supply voltage VDD such that a high output state is passed. The voltage at node D will accordingly be pulled to a voltage corresponding to VDD minus the threshold voltage V _t via the seventh transistor M7. This in turn will turn on the third transistor M3 and will pull the voltage at node tn to (VDD - Vt) - V _t = VDD - 2 V _t . As soon as the voltage at the node tn reaches the voltage corresponding to the supply voltage VDD minus the threshold voltage V _T , the third transistor M3 will turn off. The voltage at the node C will be connected to the node tn via the ninth transistor M9.

Accordingly, if the input is low, the voltages at the different nodes are shown in the following Table 3:

Table 3:

Therefore, the maximum voltages in a worst case scenario across the terminals of all of the transistors or devices are shown in the following Table 4:

Table 4:

It should be noted that all voltages are within the tolerance limit of 2,75 V of the transistors or devices. All of the threshold voltages which are used to reduce the applied voltages are back biased (body effect). Accordingly, the threshold voltage V _T increased and will reduce the applied voltage. It should furthermore be noted that no static current is present in this stable state. It should be noted that the above numbers in Table 3 and Table 4 have merely been chosen to describe the basic principles of the invention. The actual values should not be considered as restricting the principles of the invention.

Fig. 5 shows a circuit diagram of an inverter according to a third embodiment. The circuit diagram according to the third embodiment substantially corresponds to the circuit diagram according to the second embodiment. The difference between the circuit diagram according to the third embodiment to the circuit diagram according to the second embodiment is the provision of additional transistors Ml 1-M14 to avoid a possible charge build up on floating gates. The eleventh and fourteenth transistor Ml 1 and M14 are PMOS transistors and the twelfth and thirteenth transistors M 12, Ml 3 are NMOS transistors.

Therefore, the circuit diagram according to the third embodiment constitutes an improvement as compared to the circuit diagram according to the second embodiment. According to the second embodiment, when the output voltage V _OUT is high, the seventh transistor M7 is turned off once the voltage at the node D reaches the supply voltage VDD minus the threshold voltage V _t . However, any sub-threshold current in the seventh transistor M7 will raise the voltage at the node D above the voltage corresponding to the supply voltage VDD minus the threshold voltage V _t . The raising of the voltage at the node D can be avoided by coupling an eleventh transistor Ml 1 in the off state between the node D and node tgp such that a high resistance is provided. When the voltage at the node D is high, corresponding to the supply voltage minus the threshold voltage V _t , the voltage at node tgp is low and provides

a sufficient drain source voltage for the eleventh transistor Mi l. The eleventh transistor Mi l is always off and can thus act as a high resistor with respect to the voltage at the node D. Furthermore, any leakage current in the seventh transistor M7 will be compensated by the leakage in the eleventh transistor Mi l. The twelfth transistor M 12 (NMOS) is provided to avoid any sub-threshold currents on the transistor M9. The thirteenth transistor M13 (NMOS) is provided to avoid any sub-threshold currents on the transistor MlO. The fourteenth transistor M14 (PMOS) is provided to avoid any sub-threshold currents on the transistor M8. Accordingly, the twelfth transistor M12 is connected to the node C, the thirteenth transistor Ml 3 is connected to the node B and the fourteenth transistor M14 is connected to the node A such that they each act as high resistors.

The gate of the eleventh transistor Ml 1 is coupled to the supply voltage VDD, its source is connected to the node tgp and its drain is connected to the gate of the third transistor M3. The gate of the twelfth transistor M12 is coupled to VSS, its source is coupled to the node tgn and its drain is coupled to the node C, i.e. the gate of the second transistor M2. The gate of the thirteenth transistor Ml 3 is coupled to VSS while its drains is coupled to the node tn and its source is coupled to the node B, i.e. the gate of the sixth transistor M6. The gate of the fourteenth transistor M14 is coupled to the supply voltage VDD, its source is coupled to the node tp and its drain is coupled to node A, i.e. the gate of the fifth transistor M5. Fig. 6 shows a graph of a transfer function of an inverter. In particular the input voltage V _IN is depicted as solid line while the output voltage V _OUT is depicted as dotted line.

Fig. 7 shows a graph of a transfer function of an inverter as well as intermediate signals. Accordingly, the input signal VN (in), the output signal VN (out), the signal VN (tgn) at the gate tgn, the signal VN (tgp) at the node tgp, the signal VN (tn) at node tn and the signal VN (tp) at node tp are depicted.

Fig. 8 shows a graph of a transient result of the input signal, the output signal and intermediate signals. In the topmost graph, the input and output signals V _IN , V _OUT of the inverter are shown. In the middle graph, the signals at the node tgn and tgp are shown. In the bottommost graph, the signals of the nodes tn and tp are shown.

Fig. 9 shows a further graph of a transient result of the input, the output and intermediate signals for different process corners. In the topmost graph, the input and output signals of the inverter are shown. In the middle graph, the signals at the node tgn and tgp are shown. In the bottommost graph, the signals of the nodes tn and tp are shown.

Fig. 10 shows a circuit diagram of a level shifter circuit according to the fourth embodiment. The level shifter comprises two outputs V _OUTBAR and V _OUT - A first and third transistor Ml, M3 are coupled between the output V _OUT and Vss. A second and fourth transistor M2, M4 is coupled between V _OUT and a second supply voltage VDD2. A fifth and sixteenth transistor M5, M 16 are coupled between the output V _OUTBAR and Vss. A sixth and fifteenth transistor M6, M 15 is coupled between V _OUTBAR and a second supply voltage VDD2. The fifth transistor M5 is coupled between the output V _OUTBAR and a the node tgn. The sixteenth transistor M 16 is coupled between the node tgn and the Vss- An eighth transistor M8 is coupled between the gate of the fifth transistor M5 and a node between the fifthteenth and sixth transistor M 15, M6. A tenth transistor MlO is coupled between the gate of the sixth transistor M6 and a node between the fifth and sixteenth transistor M16. A fourteenth transistor M14 is coupled between the gates of the fifth and fifthteenth transistor M5, Ml 5. An eleventh transistor Ml 1 is coupled between the gates of the fourth and third transistor M4, M3. The gates of the fourteenth and the eleventh transistor M 14 and Mi l are coupled together and are coupled to VDD2. A thirteenth transistor Ml 3 is coupled between the gates of the sixth and sixteenth transistor M6, M16. A twelfth transistor M12 is coupled between the gates of the first and second transistor Ml, M2. The gates of the thirteenth and the twelfth transistor Ml 3 and M12 are coupled together and are coupled to VSS.

A seventh transistor M7 is coupled between the gate of the third transistor M3 and a node tp between the fourth and second transistor M4, M2. A ninth transistor M9 is coupled between the gate of the second transistor M2 and a node tp between the third and first transistor Ml . The gate of the fourth transistor M4 is coupled to the node between the fifthteenth and sixth transistor Ml 5, M6. The gate of the fifthteenth transistor Ml 5 is coupled to node tp. The gates of the transistors M8 and M7 are coupled to the gates of the transistors M14 and Mi l. The gates of the transistors MlO and M9 are coupled to the gates of the transistors M12 and Ml 3. The gate of the transistor Ml 6 is coupled to the input V _IN , which is coupled to an input of an inverter INVl. The inverter INVl is coupled to the supply voltage VDDl and VSS. Therefore, a level shifter is provided based on the principles of the present invention such that CMOS devices can be used with an increased signaling voltage. Accordingly, the circuits according to the first, second, third or fourth embodiment enable a usage of a low voltage process transistor or device with a higher supply voltage while still avoiding a static current consumption. The above described circuits can be implemented in mobile phones or in any other devices, which require low power circuits.

Summarizing, by using the circuits described according to the first, second, third or fourth embodiment, a 65 nm process technology providing 2,5 V process transistors which only tolerate a maximum of 2,75 voltage across their terminals can be combined with a 3,3 V signaling of their inputs and outputs, wherein the input/output voltage can rise up to 3,6 V. The principles described above are also applicable to future processes where the transistor supply voltages are scaled down. As the interfacing requirements with high voltage devices will continue to be present, the above described circuits are advantageous for upcoming processes.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. In the device claim enumerating several means, several of these means can be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Furthermore, any reference signs in the claims shall not be construed as limiting the scope of the claims.