BACKGROUND

[0001] Fluid-jet printing devices eject, or jet, fluid. For example, in the case of image-forming fluid-jet printing devices, the devices can eject fluid like ink onto print media like paper to form images on the media. In the case of three- dimensional (3D) fluid-jet printing devices, the devices can additively eject fluid like 3D print material onto a substrate to form 3D objects in a layer-by-layer manner. Fluid-jet printing devices are used in a variety of different environments, including enterprise, consumer, and print service provider (PSP) environments. A fluid-jet printing device can include replaceable components, such as printhead dies, which may be part of fluid-jet cartridges that also include supplies of fluid.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] FIG. 1 is a diagram of an example fluid-jet printhead die for a printing device. [0003] FIG. 2 is a diagram of an example fluid-jet element of a printhead die.

[0004] FIG. 3 is a diagram of an example portion of a fluid-jet printhead die. [0005] FIG. 4 is a diagram of a reading mode selection circuit of a fluid-jet printhead die. [0006] FIG. 5 is a diagram of another example portion of a fluid-jet printhead die. [0007] FIG. 6 is a diagram of an example memory element of a fluid-jet printhead die.

[0008] FIG. 7 is a diagram of an example address decoder circuit of a fluid-jet printhead die. [0009] FIG. 8 is a timing diagram of example usage of a fluid-jet printhead die in a firing mode.

[0010] FIG. 9 is a timing diagram of example usage of a fluid-jet printhead die in a first reading mode.

[0011] FIG. 10 is a timing diagram of example usage of a fluid-jet printhead die in a second reading mode.

[0012] FIG. 11 is a block diagram of an example electronic component, such as a fluid-jet printhead die.

[0013] FIG. 12 is a block diagram of an example fluid-jet printhead die.

[0014] FIG. 13 is a diagram of a non-transitory computer-readable data storage medium storing program code executable by a printing device to use the printhead die of FIG. 12.

DETAILED DESCRIPTION

[0015] As noted in the background, a fluid-jet printing device can include a replaceable printhead die, which may be part of a fluid-jet cartridge that also includes supplies of fluid for use by the device. A fluid-jet printhead die can include individually addressable fluid-jet elements, such as firing resistors, which in the case of image formation the printing device can selectively actuate, or fire, to form an image on print media as the media and the die move relative to one another. The printhead die directly or indirectly interfaces with the printing device via conductive pads.

[0016] A fluid-jet printhead die may include memory elements, such as non-volatile memory (NVM) elements, which can store information like serial numbers, manufacturing dates, and so on. The NVM elements may be read-only memory (ROM) elements, such as programmable ROM (PROM) elements, which may be in the form of programmable links. The programmable links may be manufactured in the open state and selectively irreversibly closed via fusing or in another manner, may be manufactured in the closed state and selectively irreversibly opened via fusing or in another manner, or may be selectively manufactured in open and closed states. Such memory elements are binary memory elements, in that they can each store a logic zero or a logic one depending on whether their programmable links are open or closed.

[0017] The memory elements of a fluid-jet printhead may be individually and correspondingly connected to the same address lines by which the fluid-jet elements are addressable. For example, each memory element may be selected by asserting the address line to which it is connected. A fluid-jet printhead die having M address lines can thus have M individually addressable memory elements, providing a total of M bits of data storage. [0018] Given types of fluid-jet printing devices are compatible with given types of printhead dies. For a printhead die to be compatible with a fluid-jet printing device, the printhead die has to be able to properly interface with the printing device, among other things. For example, if the die is part of a fluid-jet cartridge, the cartridge has to physically fit within or otherwise connect to the printing device, with conductors of the cartridge that are connected to conductive pads of the die making electrical contact with corresponding conductors of the device. A printhead die may have a conductive pad for each of its address lines, which interfaces with a corresponding conductive pad of the cartridge of which it is a part, and which in turn makes electrical contact with a corresponding conductor of the device to which the cartridge is connected.

[0019] Adding capabilities or extra functionality to a fluid-jet printhead die while retaining backwards compatibility with a given type of fluid-jet printing device is therefore difficult without adding or replacing hardware within the printing device. More specifically, adding readable data storage to a printhead die while retaining such backwards compatibility can be difficult without adding or replacing hardware within the printing device. The printing device may have to communicate with the printhead die in a particular way to read the additional data storage. However, such communication is limited to the existing electrical interface between the printhead die and the device. For instance, existing conductive pads used for data input may not be able to be used for data output, and vice versa, to maintain compatibility. Furthermore, additional conductive pads may not be able to be added to maintain compatibility. [0020] Techniques described herein provide ways by which more readable data storage can be added to a fluid-jet printhead die for use within a fluid-jet printing device without having to add or replace hardware within the printing device. The printhead die includes address lines and fluid-jet elements that are organized in groups correspondingly connected to the address lines. The printhead die includes (additional) memory elements that are binary addressable on an address subset of the address lines, and which are read in a reading mode selected or entered via the printing device selectively asserting in a specified manner a selection subset of more than one of the address lines.

[0021] The fluid-jet printhead die includes address pads that are correspondingly connected to the address lines and that interface the die with the printing device. The address pads can configurationally correspond to the address pads of a legacy fluid-jet printhead die lacking the memory elements that are binary addressable on the address subset of the address lines. For example, the memory elements may be in addition to legacy memory elements that are each connected to a corresponding address line, and that are individually selected via individual assertion of their corresponding address lines. The printhead die can thus be backwards compatible in that the printing device can read the legacy memory elements no differently than if the die were a legacy fluid-jet printhead die lacking the additional memory elements.

[0022] For instance, a fluid-jet printing device may use a particular type of legacy fluid-jet printhead die lacking the additional memory elements but having the legacy memory elements. The printing device may individually assert the legacy printhead die’s address lines (i.e. , one at a time) via their corresponding address pads on the die when reading the legacy memory elements (as well as when selectively firing the die’s fluid-jet elements). Since the address pads of the disclosed fluid-jet printhead die can configurationally correspond to the legacy printhead die’s address pads, the disclosed die can still be used in such a printing device, even if the device is unable to read the additional memory elements.

[0023] A fluid-jet printing device may thus be upgradeable to read the additional memory elements without having to replace or add hardware in the printing device. The additional memory elements of the printhead die are addressable over the same address lines that are used when reading the legacy memory elements, with the difference being that more than one address line is asserted when reading the additional memory elements. A printing device that is compatible with a legacy fluid-jet printhead die with which the disclosed printhead die’s address pads configurationally correspond can therefore be programmed to use the disclosed die’s additional memory elements, so long as the device’s firmware or other software is upgradable.

[0024] FIG. 1 shows an example fluid-jet printhead die 100 for a fluid-jet printing device. For example, the printhead die 100 may be an inkjet printhead die for an inkjet-printing device. The printhead die 100 is more generally an electronic component, and the printing device is more generally an electronic device. Therefore, the printhead die 100 is more generally an electronic component for an electronic device. The printhead die 100 includes fluid-jet elements 102, which can be organized over rows 104 and columns 106, as in the example of FIG. 1. The rows 104 of the fluid-jet elements 102 can more generally be referred to as groups, whereas the columns 106 can more generally be referred to as primitives. The fluid-jet elements 102 are individually addressable, and are actuated or fired to cause the elements 102 to eject fluid, like ink.

[0025] The fluid-jet printhead die 100 includes an M-bit address bus 108 made up of M one-bit address lines 110A, 110B, . . ., 110M, which are collectively referred to as the address lines 110. The address lines 110 are correspondingly connected to the rows 104 of the fluid-jet elements 102. That is, each address line 110 is connected to the fluid-jet elements 102 within a corresponding row 104, with each address line 110 connected to a different row 104 of the elements 102. The number or rows 104 can therefore be equal to the number of address lines 110, and is more generally equal to or less than the number of address lines 110.

[0026] The fluid-jet printhead die 100 includes an N-bit primitive bus 112 made up of N one-bit primitive lines 114A, 114B, . . ., 114N, which are collectively referred to as the primitive lines 114. The primitive lines 114 are correspondingly connected to the columns 106 of the fluid-jet elements 102.

That is, each primitive line 114 is connected to the fluid-jet elements 102 within a corresponding column 106 of the elements 102, with each primitive line 114 connected to a different column 106 of the elements 102. The number of columns 106 can therefore be equal to the number of primitive lines 114, and more generally is equal to or less than the number of primitive lines 114. The N number of primitive lines 114 can be equal to, less than, or greater than the M number of address lines 110. [0027] Assertion of an address line 110 selects the fluid-jet elements 102 connected to the row 104 to which the address line 110 corresponds. Likewise, assertion of a primitive line 114 selects the fluid-jet elements 102 connected to the column 106 to which the primitive line 114 corresponds. Each fluid-jet element 102 is therefore individually addressable via assertion of both the address line 110 connected to the row 104 including the element 102 and the primitive line 114 connected to the column 106 including the element 102. [0028] The fluid-jet printhead die 100 includes M address pads 116 connected to the address bus 108 and thus correspondingly connected to the address lines 110. Each address pad 116 is connected to a different address line 110 of the address bus 108. The fluid-jet printhead die 100 includes N primitive pads 118 connected to the primitive bus 112 and thus correspondingly connected to the primitive lines 114. Each primitive pad 118 is connected to a different primitive line 114 of the primitive bus 112. [0029] The fluid-jet printhead die 100 interfaces with a printing device via the address pads 116 and the primitive pads 118. For instance, wires or other types of conductive traces may conductively connect the pads 116 and 118 of the printhead die 100 to corresponding pads on the printing device. As another example, the printhead die 100 may be part of a fluid-jet cartridge that also includes supplies of fluid. Wires or other types of conductive traces may conductively connect the pads 116 and 118 of the printhead die 100 to the cartridge, with the cartridge then making conductive contact with the printing device upon insertion into or connection to the device. The printhead die 100 may include pads other than the address pads 116 and the primitive pads 118. [0030] In a firing mode, the fluid-jet printhead die 100 selectively ejects fluids from the fluid-jet elements 102. In the firing mode, the printing device individually asserts the address lines 110 one at a time, to correspondingly select the rows 104 of the fluid-jet elements 102 one row at a time. While asserting a given address line 110, the printing device also selectively asserts the primitive lines 114, to correspondingly select the columns 106 of the fluid-jet elements 102. The fluid-jet elements 102 within the selected row 104 and the selected columns 106 (i.e. , each element 102 is connected to the asserted address line 110 as well as to any asserted primitive line 114) is thus actuated or fired, causing fluid to be ejected from the die 100. The fluid-jet elements 102 can include non-ejecting such elements as well, which function as microfluidic pumps that when actuated or fired displace, pump, or transfer fluid elsewhere within the die 100. [0031] The fluid-jet printhead die 100 may include M memory elements

120, which are correspondingly connected to the address lines 110 of the address bus 108. That is, each memory element 120 is connected to a different address line 110. The number of memory elements 120 can therefore be equal to the number of address lines 110, and is more generally equal to or less than the number of address lines 110. Assertion of an address line 110 selects the memory element 120 to which the asserted address line 110 is connected, permitting the selected memory element 120 to be read in a first reading mode of the printhead die 100. [0032] The memory elements 120 may be legacy memory elements. For example, the memory elements 120 may be the same type of memory elements present on a legacy fluid-jet printhead die with which the fluid-jet printhead die 100 is backwards compatible. In such an implementation, the memory elements 120 can therefore be read in the first reading mode by a printing device to which the printhead die 100 is connected no differently than the memory elements of a legacy printhead die to which the memory elements 120 correspond.

[0033] The fluid-jet printhead die 100 includes 2^ or fewer memory elements 122 that are binary addressable via an address subset 142 of J<M-1 address lines 110 of the address bus 108. The address subset 142 can include as few as one address line 110. Because the memory elements 122 are binary addressable on the address subset 142 of the address lines 110, the number of memory elements 122 can be equal to two the power of the J number of address lines 110 within the subset 142. Encoding or loading a binary address on the address subset 142 of the address lines 110 via selective assertion of the subset 142 selects the memory element 122 having the encoded binary address, permitting the selected element 122 to be read in a second reading mode of the die 100.

[0034] The memory elements 122 may be the same type of memory elements as the memory elements 120. For example, the memory elements 122 may be binary memory elements that can each store a logic one or a logic zero. Flowever, in other implementations, the memory elements 122 may be a different type of memory elements than the memory elements 120. For instance, the memory elements 122 may be non-binary memory elements that can each store one of more than two different values. A ternary memory element can store one of three different values, whereas a quaternary memory element can store one of four different values. [0035] The memory elements 120 and 122 may be NVM elements, such as ROM elements like PROM elements. The memory elements 120 and/or 122 further may be rewritable ROM elements, such as erasable PROM (EPROM) elements like electrically erasable PROM (EEPROM) elements, or may be volatile memory elements. For example, the memory elements 120 may be legacy memory elements that are PROM elements, whereas the memory elements 122 may be rewritable ROM elements or volatile memory elements. [0036] The fluid-jet printhead die 100 includes memory pads 124 and 126 and enable switches 128 and 130. The enable switch 128 and the memory elements 120 are connected (e.g., by one line) in series between the memory pads 124 and 126, as are the enable switch 130 and the memory elements 122. The enable switch 128 controls enablement of the memory elements 120 for reading. The series branch of the enable switch 128 and the memory elements 120 and the series branch of the enable switch 130 and the memory elements 122 are in parallel to one another between the memory pads 124 and 126. The enable switch 130 controls enablement of the memory elements 122 for reading. [0037] As with the address pads 116 and the primitive pads 118, the fluid- jet printhead die 100 interfaces with a printing device via the memory pads 124 and 126. For instance, wires or other types of conductive traces may conductively connect the memory pads 124 and 126 of the fluid-jet printhead die 100 to corresponding pads on the printing device. As another example, the printhead die 100 may be part of a fluid-jet cartridge that also includes supplies of fluid. Wires or other types of conductive traces may conductively connect the memory pads 124 and 126 to the cartridge, with the cartridge then making conductive contact with the printing device upon insertion into or connect to the device. The printhead die 100 may include pads other than the memory pads 124 and 126 (as well as other than the address pads 116 and the primitive pads 118). [0038] The fluid-jet printhead die 100 includes a reading mode selection circuit 132, which is connected to a selection subset 134 of K<M-J address lines 110 of the address bus 108. The selection subset 134 includes more than one address line 110. The address lines 110 of the selection subset 134 are different than the address lines of the address subset 142. That is, any address line 110 that is part of the selection subset 134 is not part of the address subset 142, and vice-versa. There may be address lines 110 that are not part of either subset 134 or 142. As such, J+K<M, with 2<K<M-J and J<M-1 (i.e., J£M-2).

[0039] The reading mode selection circuit 132 selects the first reading mode, in which the memory elements 120 can be read, or the second reading mode, in which the memory elements 122 can be read, depending on whether the selection subset 134 of the address lines 110 is selectively asserted in a specified manner or not. If the selection subset 134 is not selectively asserted in the specified manner, then the first reading mode is selected. If the selection subset 134 is selectively asserted in the specified manner, then the second reading mode is selected. That the selection subset 134 is asserted in a specified manner means that two or more address lines 110 within the subset 134 are specifically asserted, and that one or more address lines within the subset 134 are specifically not asserted.

[0040] An address line 110 being asserted means that the address line 110 is driven to a first state, and an address line 110 not being asserted means that the address line 110 is driven to a second state. For example, driving an address line 110 to a first state may mean that a higher voltage is applied to the address line 110, and driving the address line 110 to a second state may mean that a lower voltage is applied to the address line 110. The first and second states may respectively correspond to logic one and logic zero, or vice-versa. [0041] The specified manner in which the address lines 110 of the selection subset 134 are asserted may be a specific pattern of the address lines 110 of the subset 134, such as all the address lines 110 of the subset 134 being asserted. In this case, in response to every address line 110 of the selection subset 134 being asserted, then the second reading mode is selected. In response to any address line 110 of the subset 134 not being asserted, then the first reading mode is selected. [0042] In another example, the specified pattern may be the first, second, and fourth address lines 110 being asserted, where there are four address lines 110 within the selection subset 134. In this case, in response to the first, second, and fourth address lines 110 of the selection subset 134 being asserted, and the third address line 110 of the subset 134 not being asserted, then the second reading mode is selected. If any of the first, second, and fourth address lines 110 of the selection subset 134 is not asserted, or if the third address line 110 of the subset 134 is asserted, then the first reading mode is selected. In general, the number of address lines 110 of the selection subset 134 that have to be asserted (as opposed to not being asserted) per the specified manner is more than one.

[0043] The reading mode selection circuit 132 is communicatively connected to the enable switches 128 and 130 via respective enable lines 136 and 138. The enable line 136 controls the enable switch 128, and the enable line 138 controls the enable switch 130. If the selection subset 134 of the address lines 110 is not selectively asserted in the specified manner, then the reading mode selection circuit 132 asserts the enable line 136 controlling the enable switch 128, selecting the first reading mode and permitting selective reading of the memory elements 120. If the selection subset 134 of the address lines 110 is selectively asserted in the specified manner, then the reading mode selection circuit 132 asserts the enable line 138 controlling the enable switch 130, selecting the second reading mode and permitting selective reading of the memory elements 122. [0044] The fluid-jet printhead die 100 includes an address decoder circuit

140 connected to the address subset 142 of J<M-1 address lines 110 of the address bus 108. The address decoder circuit 140 is selectively connected to the memory elements 122 via H memory lines 144. The address decoder circuit 140 decodes the binary address encoded on the address lines 110 of the address subset 142 to correspondingly assert the memory lines 144 specifically connected to the memory element 122 having the encoded binary address. [0045] For example, the memory elements 122 may be organized within an array of rows and columns, which are more generally first groups and second groups, and which are correspondingly connected to the memory lines 144. A memory line 144 is connected to each row and to each column, such that the H number of memory lines 144 can equal the number of rows plus the number of columns. The address decoder circuit 140 decodes the binary address encoded on the address subset 142 of the address lines 110 to the row and column including the memory element 122 having the encoded binary address. The address decoder circuit 140 thus asserts the memory line 144 connected to the row of this memory element 122 and the memory line 144 connected to the column of this memory element 122, to select the element 122 for reading in the second reading mode.

[0046] The printing device to which the printhead die 100 is connected measures impedance between the memory pads 124 and 126 to read the selected memory element 120 in the first reading mode or the selected memory element 122 in the second reading mode. The impedance between the memory pads 124 and 126 corresponds to the value stored on the selected memory element 120 or 122. The memory pads 124 and 126 may be present within the printhead die 100 for legacy reasons, such as to provide a way to measure analog signals on the die 100, and in this case are leveraged to read the value stored on the selected memory element 120 or 122.

[0047] For instance, the printing device can inject a given current at the memory pad 124, with the memory pad 126 connected to electrical ground, and measure the voltage drop over the selected memory element 120 or 122. The measured voltage drop corresponds to the value stored on the selected memory element 120 in the first reading mode and to the value stored on the selected memory element 122 in the second reading mode. This is because the resistance of the selected memory element 120 or 122 is dependent on the value stored on the memory element 120 or 122.

[0048] In operation of the fluid-jet printhead die 100, the printing device to which the printhead die 100 is connected fires a selected fluid-jet element 102 in the firing mode by asserting the address line 110 and the primitive line 114 respectively connected to the row and the column (i.e. , the group and the primitive) including the fluid-jet element 102. The printing device can also read the memory element 120 connected to the asserted address line 110 at this time, in which case the first reading mode coincides with the firing mode. However, the printing device can assert the address line 110 connected to a selected memory element 120 while no primitive line 114 is asserted to read the selected memory element 120 in the first reading mode. In this case, the first reading mode does not coincide with the firing mode.

[0049] In either case, the first reading mode and not the second reading mode of the fluid-jet printhead die 100 is selected because the printing device has asserted just one address line 110. Because just one address line 110 is asserted, the selection subset 134 of the address lines 110 will not have been selectively asserted in any specified manner, since the subset 134 includes more than one of the address lines 110. Therefore, the reading mode selection circuit 132 asserts the enable line 136 controlling the enable switch 128 connected to the memory elements 120 to enter the first reading mode, and not the enable line 138 controlling the enable switch 128 connected to the memory elements 122 and that controls entry into the second reading mode.

[0050] In the second reading mode, by comparison, the printing device selectively asserts the selection subset 134 of the address lines 110 in the specified manner while encoding or loading the binary address of a selected memory element 122 on the address subset 142 of the address lines 110, and while no primitive line 114 is asserted, to read the selected memory element 122. Although the memory elements 120 connected to the asserted address lines 110 of the subsets 134 and 142 are also implicitly selected, the selected elements 120 cannot be read. Because the printing device has selectively asserted the selection subset 134 of the address lines 110 in the specified manner, the reading mode selection circuit 132 asserts the enable line 138 controlling the enable switch 130 connected to the memory elements 122 to enter the second reading mode, and not the enable line 136 controlling the enable switch 128 connected to the memory elements 120 and that controls entry into the first reading mode. [0051] However, the printing device reads the selected memory element 120 in the first reading mode and the second memory element 122 in the second reading mode in the same manner. Specifically, as noted above, the printing device can measure the impedance between the memory pads 124 and 126, such as by measuring the voltage drop over the selected memory element 120 or 122. As also noted above, the measured impedance corresponds to the value stored on the selected memory element 120 or 122.

[0052] FIG. 2 shows an example implementation of a fluid-jet element 102 of the fluid-jet printhead die 100. The fluid-jet element 102 includes a firing resistor 202 and a transistor 204 in series with one another, between a primitive line 114 and ground. The firing resistor 202 can also be referred to as a heating resistor. The transistor 204 has its gate connected to an address line 110.

[0053] Assertion of the address line 110 and the primitive line 114 selects and thus fires the fluid-jet element 102, causing current to flow through the firing resistor 202. When current flows through the firing resistor 202, the resistor 202 increases in temperature. This temperature increase in turn heats fluid surrounding the firing resistor 202, forming a bubble within the fluid, which results in ejection of a droplet of the fluid from fluid-jet element 102.

[0054] FIG. 3 shows an example portion 300 of a fluid-jet printhead die. The example portion 300 specifically shows an example implementation of the memory elements 120 and the enable switch 128 of the printhead die 100 of FIG. 1. As in FIG. 1 , the memory elements 120 and the enable switch 128 are in a series branch between the memory pads 124 and 126. [0055] The memory elements 120 include M memory elements 120A,

120B, . . 120M, which are correspondingly connected to the address lines 110A,

110B, . . 110M. The memory elements 120 are in parallel between the enable switch 128 and the memory pad 126. In the example of FIG. 3, each memory element 120 includes a programmable link 304 in series with a transistor 306 having its gate connected to a corresponding address line 110. The programmable link 304 may be manufactured in the open state and selectively irreversibly closed via fusing or in another manner, or may be manufactured in the closed state and selectively irreversibly opened via fusing or in another manner. Assertion of an address line 110 turns on the transistor 306 of a corresponding memory element 120, permitting current to flow through the element 120.

[0056] The enable switch 128 in the example of FIG. 3 includes a transistor 302. The gate of the transistor 302 is connected to the enable line 136. Assertion of the enable line 136 turns on the transistor 302, permitting current to flow through the transistor 302.

[0057] FIG. 4 shows an example implementation of the reading mode selection circuit 132 of the fluid-ejection printhead die 100 of FIG. 1. In the example of FIG. 4, the specified manner in which the selection subset 134 is selectively asserted to enter the extra functionality mode is the assertion of every address line 110 within the selection subset 134. The selection circuit 132 thus can include a logical AND gate 402, which can be implemented as a discrete electronic component or as part of a complex electronic component like an integrated circuit (1C).

[0058] The logical AND gate 402 is more generally a logic circuit. The address lines 110 of the selection subset 134 are input to the logical AND gate 402. If the specific manner in which the selection subset 134 is selectively asserted is other than assertion of every address line 110 within the subset 134, then each address line 110 that is to remain unasserted may be connected to the logical AND gate 402 via an intervening inverter.

[0059] The output of the AND gate 402 is the enable line 138 that controls entry into the second reading mode in FIG. 1. That is, the non-inverted output of the logical AND gate 402 thus controls the enable switch 130 of FIG. 1. An inverter 404 is connected to the output of the AND gate 402 to provide the enable line 136 that controls entry into the first reading mode in FIG. 1. That is, the inverted output of the logical AND gate 402 thus controls the enable switch 128 of FIG. 1.

[0060] In the example of FIG. 4, when every address line 110 of the selection subset 134 is asserted, the reading mode selection circuit 132 asserts the enable line 138, causing entry into the second reading mode, because the output of the logical AND gate 402 is at a first state. If any address line 110 of the selection subset 134 is not asserted, the reading mode selection circuit 132 asserts the enable line 136, causing entry into the first reading mode, because the output of the AND gate 402 is at a second state. In this way, either the first reading mode or the second reading mode is selected, and not both reading modes simultaneously.

[0061] FIG. 5 shows an example portion 500 of a fluid-jet printhead die.

The example portion 500 specifically shows an example implementation of the memory elements 122 and the enable switch 130 of the printhead die 100 of FIG. 1. As in FIG. 1, the memory elements 122 and the enable switch 130 are in a series branch between the memory pads 124 and 126.

[0062] In the example of FIG. 5, the memory elements 122 are organized in X rows 506 and Y columns 508; more generally, the memory elements 122 can be organized in first groups and second groups. The rows 506 of the memory elements 122 are correspondingly connected to X memory row lines 510. That is, each row 506 is connected to a different row line 510. The columns 508 of the memory elements 122 are connected to Y column switches 502 that are correspondingly controlled by Y memory column lines 512. That is, each column switch 502 is controlled by a different column line 512. The column switches 502 can more generally be referred to as second group switches. In the example of FIG. 5, each column switch 502 is implemented as a transistor 504 having its gate connected to a corresponding column line 512. Assertion of a column line 512 turns on and thus permits current to flow through the transistor 504 connected to the column line 512 in question.

[0063] The enable switch 130 is connected between the memory pad 124 and every column switch 502. The enable switch 130 in the example of FIG. 5, like the enable switch 128 in FIG. 3, includes a transistor 514. The gate of the transistor 504 is connected to the enable line 138. Assertion of the enable line 138 turns on the transistor 514, permitting current to flow through the transistor 514.

[0064] The address decoder circuit 140 is connected to the address subset 142 of address lines 110 of FIG. 1. In the example of FIG. 5, the address decoder circuit 140 decodes, or converts, a binary address loaded or encoded on the address subset 142 into the row 506 and the column 508 including the memory element 122 addressable by (i.e. , having) the binary address. The address decoder circuit 140, via the column lines 512, thus controls the column switches 502. The address decoder circuit 140 specifically asserts the row line 510 connected to the row 506 including this memory element 122, and the column line 512 connected to the column 508 including this element 122. If the enable line 138 has also been asserted, current can therefore flow through the selected memory element 122 between the memory pads 124 and 126. [0065] The memory row lines 510 and the memory column lines 512 can constitute the memory lines 144 of FIG. 1. Therefore, the number X of row lines 510 plus the number Y of column lines 512 can equal the number FI of memory lines 144 in FIG. 1. Because there can be 2^ memory elements 122 addressable on the subset 144 of J memory lines 110 in FIG. 1 , 2^ = X * Y . [0066] FIG. 6 shows an example implementation of a memory element

122 of the fluid-jet printhead die 100. The memory element 122 can be implemented similar to each memory element 120 in FIG. 3. The memory element 122 includes a programmable link 602 in series with a transistor 604. The programmable link 602 is connected to the column switch of the column including the memory element 122, as well as to the next memory element in the same column, if any. The transistor 604 is connected to the memory pad 126. [0067] The programmable link 602 is more generally a storage element that can store a value. The storage element may be a binary storage element that can store one of two values, such as logic one and logic zero. The storage element may be a non-binary storage element, such as a tertiary storage element that can store one of three values, and so on. The storage element may be an analog storage element instead of a digital storage element as well. Other examples of storage elements include fuses, anti-fuses, erasable programmable read-only memory (EPROM), electrically EPROM (EEPROM), and so on.

[0068] In one implementation, the programmable link 602 may be manufactured in the open state and selectively irreversibly closed via fusing or in another manner, may be manufactured in the closed state and selectively irreversibly opened via fusing or in another manner, or may be selected manufactured in open and closed states. The open and closed states are more generally first and second states. The gate of the transistor 604 is connected to the memory row line 510 corresponding to the row including the memory element 122. Assertion of the row line 510 turns on the transistor 604 of the memory element 120, permitting current to flow through the element 120 if the column switch of the column including the element 120 has also been turned on.

[0069] FIG. 7 shows an example address decoder circuit 700 for a fluid-jet printhead die. The address decoder circuit 700 can implement the address decoder circuit 140 of the fluid-jet printhead die 100 of FIG. 1 , specifically in the case in which the memory elements 122 are organized within an array of rows 506 and columns 508 as in FIG. 5. The address decoder circuit 700 includes a row decoder circuit 702 and a column decoder circuit 704. The address decoder circuit 140 may be implemented in a manner other than as the address decoder circuit 700, and further the row and address decoder circuits 702 and 704 may be implemented in a manner other than as depicted in FIG. 7.

[0070] In the implementation of FIG. 7, the address subset 142 includes

J=4 address lines 110, permitting a total of 2^=16 memory elements to be individually addressed via binary addresses encoded on the address lines 110.

In the example of FIG. 7, there are four memory row lines 510 and four memory column lines 512, meaning that the binary addressable memory elements are organized in an array of four rows and four columns.

[0071] The row decoder circuit 702 and the column decoder circuit 704 are each implemented in the same manner in FIG. 7. The row decoder circuit 702 decodes two of the four bits of the four-bit address encoded on the address lines 110 into a row, asserting the memory row line 510 corresponding to the decoded row. Likewise, the column decoder circuit 704 decodes the other two of the four bits of the four-bit address encoded on the address lines 110 into a column, asserting the memory column line 512 corresponding to the decoded column. [0072] Each of the decoder circuits 702 and 704 includes four logical AND gates 706. The outputs of the logical AND gates 706 of the row decoder circuit 702 correspond to the memory row lines 510, whereas the outputs of the logical AND gates 706 of the column decoder circuit 704 correspond to the memory column lines 512. Each AND gate 706 has two inputs. Each input is connected to an address line 110 or an inverter 708 that is itself connected to an address line 110, as specifically shown in FIG. 7. [0073] As such, a four-bit value is encoded on the address lines 110 via selective assertion of the address lines 110. Based on the selective assertion of the two address lines 110 input into the row decoder circuit 702, one of the logical AND gates 706 of the decoder circuit 702 asserts its corresponding memory row line 510. Similarly, based on the selective assertion of the other two address lines 110 input into the column decoder circuit 704, one of the logical AND gates 706 of the decoder circuit 704 asserts its corresponding memory column line 512.

[0074] FIG. 8 shows a timing diagram of example usage of the fluid-jet printhead die 100 of FIG. 1 in a firing mode, by a fluid-jet printing device connected to the printhead die 100. In the example of FIG. 8, there are four address lines 110 and four primitive lines 114 within the printhead die 100 under control of the printing device. The printing device individually asserts the address lines 110 in succession in the firing mode.

[0075] The address lines 110 may be addressable via four bits, with each bit corresponding to a different address line 110. In the example of FIG. 8, a logic one corresponds to an address line 110 being asserted, whereas a logic zero corresponds to an address line 110 not being asserted; in other implementations, the mapping between assertion/not assertion and logic values can vary. Therefore, the addresses 0001, 0010, 0100, 1000 are consecutively loaded onto the address lines 110 to successively and individually assert the address lines 110. While each address line 110 is asserted, the printing device also selectively asserts the primitive lines 114. [0076] The primitive lines 114 may also be addressable via four bits, with each bit corresponding to a primitive line 114, a logic one corresponding to a primitive line 114 being asserted, and a logic zero corresponding to a primitive line 114 not being asserted. Therefore, primitives are consecutively loaded onto the primitive lines 114 as the address lines 100 are individually asserted to selectively assert the primitive lines 114. This is indicated by the primitives ???? in FIG. 8, since which primitive lines 114 are asserted differs depending on which primitive lines 114 are selected.

[0077] As such, in the firing mode of the fluid-jet printhead die 100, the printing device selectively and individually asserts the address lines 110 and selectively asserts the primitive lines 114 to selectively fire the fluid-jet elements. For a given row, or first group, of fluid-jet elements selected via assertion of its corresponding address line 110, the elements within that row that are also within columns, or second groups, selected via assertion of their corresponding primitive lines 114 are selected. These selected fluid-jet elements are therefore fired and eject fluid from the printhead die 100.

[0078] A first reading mode, in which the memory elements 120 of FIG. 1 can be read, can coincide with the firing mode in the example of FIG. 8. As the address lines 110 are individually asserted in succession to selectively fire the fluid-jet elements connected to the address lines 110, the memory elements 120 are also correspondingly individually selected. Therefore, the printing device can read the memory elements 120 as the elements 120 are individually selected, by measuring the impedance between the memory pads 124 and 126 of FIG. 1 as has been described.

[0079] FIG. 9 shows a timing diagram of example usage of the fluid-jet printhead die 100 in a first reading mode that does not coincide with a firing mode, by a fluid-jet printing device connected to the printhead die 100. In the example of FIG. 9, there are again four address lines 110 and four primitive lines 114 within the printhead die 100. FIG. 9 also shows the enable lines 136 and

138 of the printhead die 100, which have been described in relation to FIG. 1. [0080] The printing device individually asserts the address lines 110 in succession in the first reading mode, as in FIG. 8. Flowever, in the example of FIG. 9, the printing device does not assert the primitive lines 114 in the first reading mode. As such, the first reading mode does not coincide with the firing mode in FIG. 9, since no fluid-jet elements of the printhead die 100 are selected and thus none of the fluid-jet elements will fire.

[0081] Individual assertion of the address lines 110 results in the reading mode selection circuit 132 of FIG. 1 asserting the enable line 136 and not the enable line 138. This is because no more than one address line 110 is asserted at a time. Therefore, the memory element 120 of FIG. 1 connected to the address line 110 is selected, and not any of the memory elements 122 of FIG. 1. The printing device can read the selected memory element 120 by measuring the impedance between the memory pads 124 and 126 of FIG. 1 as has been described.

[0082] In the examples of FIGs. 8 and 9, the printing device may be incapable of or otherwise unable to read the memory elements 122 of FIG. 1 that are read in the second reading mode via selectively assertion of the address lines 110 of the selection subset 134 of FIG. 1 in a specified manner. That is, the printing device may be unable to use the second reading mode of the printhead die 100. Nevertheless, the printing device is still able to use the firing mode and the first reading mode of the printhead die 100. Therefore, FIGs. 8 and 9 show how a printhead die 100 that has the memory elements 122 can still nevertheless be backwards compatible with printing devices that cannot take advantage of such extra functionality, as if the printhead die 100 were a legacy printhead die lacking the memory elements 122 and thus lacking the second reading mode. [0083] FIG. 10 shows a timing diagram of example usage of the fluid- jet printhead die 100 in a second reading mode, by a fluid-jet printing device connected to the printhead die 100. In the example of FIG. 10, there are again four address lines 110 and four primitive lines 114 within the printhead die 100. As in FIG. 9, FIG. 10 shows the enable lines 136 and 138 of the printhead die 100. [0084] In the example of FIG. 10, the lowest two bits of the address loadable on the address lines 110 correspond to the address lines 110 of the selection subset 134 of FIG. 1. The highest two bits of the address correspond to the address lines of the address subset 142 of FIG. 1. In the second reading mode, the printing device individually asserts the address lines 110 of the address subset 142 while asserting both address lines 110 of the selection subset 134, and while not asserting the primitive lines 114.

[0085] In the example, assertion of both the address lines 110 of the selection subset 134 of FIG. 1 results in the reading mode selection circuit 132 of FIG. 1 asserting the enable line 138 and not the enable line 136. The memory element 122 of FIG. 1 addressable by the address loaded on the address lines 110 of the address subset 142 of FIG. 1 is thus selected. The printing device can read the selected memory element 122 by measuring the impedance between the memory pads 124 and 126 of FIG. 1 as has been described.

[0086] In the examples of FIGs. 9 and 10, the memory elements 120 and

122 are respectively read in succession. In FIG. 9, the memory elements 120 are successively read via successive individual assertion of the address lines 110. In FIG. 10, the memory elements 122 are successively read via successive loading of their corresponding addresses on the address subset 142 of the address lines 110 while asserting the selection subset 134 of the address lines 110. Flowever, the memory elements 120 and 122 do not have to be successively read. The memory elements 120 can be selected in any order for reading in FIG. 9, and the memory elements 122 can be selected in any order for reading in FIG. 10.

[0087] In the examples of FIGs. 9 and 10, the printing device does not assert any of the primitive lines 114. In another implementation, however, the printhead die 100 may have circuitry that is enabled specifically in the second reading mode. This circuitry may prevent the fluid-jet elements from being fired. Therefore, in such an implementation, even if the printing device inadvertently asserts any primitive line 114, no fluid-jet elements will be fired.

[0088] FIG. 11 shows an example electronic component 1100 for an electronic device. The electronic component 1100 may be a fluid-jet printhead die for a fluid-jet printing device as has been described, for instance. The electronic component 1100 includes address lines 1102 and memory elements 1104 correspondingly connected to the address lines 1102. Assertion of an address line 1102 selects the memory element 1104 connected to the asserted address line 1102 in a first reading mode. There may be M address lines 1102 and M memory elements 1104.

[0089] The electronic component includes memory elements 1106 that are binary addressable on an address subset of the address lines 1102. Selective assertion of a selection subset of the address lines 1102 in a specified manner selects the memory element 1106 having a binary address encoded on the address subset of the address lines 1102 in a second reading mode. There may be J<M-1 address lines 1102 within the address subset. There may be 2<K<M-J address lines 1102 within the selection subset. There may be 2^ memory elements 1106. [0090] FIG. 12 shows an example fluid-jet printhead die 1200 for a printing device. The printhead die 1200 includes address lines 1202 and fluid-jet elements 1204 organized in groups, such as rows, correspondingly connected to the address lines 1202. There may be M address lines 1202 and M groups or rows of fluid-jet elements 1204. The printhead die 1200 includes address pads 1206 correspondingly connected to the address lines 1202 to interface the die with the printing device. There may be M address pads 1206.

[0091] The printhead die 1200 includes memory elements 1208 that are binary addressable on an address subset of the address lines 1202. Selective assertion of a selection subset of the address lines 1202 in a specified manner selects the memory element 1208 having a binary address encoded on the address subset of the address lines 1202 in a reading mode. There may be J<M-1 address lines 1202 within the address subset. There may be 2<K<M-J address lines 1102 within the selection subset. There may be 2^ memory elements 1208.

[0092] FIG. 13 shows an example non-transitory computer-readable data storage medium 1300. The computer-readable data storage medium 1300 stores program code 1302. The program code 1302 is executable by a printing device connected to a fluid-jet printhead die having fluid-jet elements organized within groups, such as first groups and second groups like rows and columns, to perform processing.

[0093] The processing includes, in a firing mode (1304), individually asserting address lines correspondingly connected to the rows or other groups to select the fluid-jet elements within the row connected to the asserted address line (1306). The processing includes, in the firing mode (1304), while each address line is individually asserted, selectively asserting primitive lines correspondingly connected to the columns (or other primitives) to select the fluid-jet elements within the columns connected to the asserted primitive lines (1308). The fluid-jet elements connected to the asserted address line and the asserted primitive lines fire.

[0094] The processing includes, in a reading mode (1310), selectively asserting a selection subset of the address line in a specified manner (1312), which selects the reading mode. The processing includes, in the reading mode (1310), encoding a binary address of a selected memory element of a number of memory elements of the die on an address subset of the address lines (1314). The processing includes, in the reading mode, sensing an impedance between pads on the die, the impedance corresponding to a value stored by the selected memory element (1316). For example, the impedance between the pads may be sensed by sensing or measuring a voltage drop over the selected memory element.

[0095] The printhead die can include other memory elements, which are correspondingly connected to the address lines. The other memory elements may be readable in a different reading mode, which may coincide with the firing mode. In this reading mode, the printing device asserts just the address line connected to a memory element, and senses the voltage drop over the selected memory element, with the voltage drop again corresponding to a value stored by the selected memory element.

[0096] A fluid-jet printhead die, which is more generally an electronic component, has been described that has a reading mode to read memory elements on the die. The reading mode is selected using the same address lines that are used to select fluid-ejection elements of the printhead die in a firing mode. Whereas the firing mode is selected via individual assertion of the address lines, the reading mode is selected via selectively assertion of more than one address line, specifically the address lines of a selection subset. The memory element having a binary address encoded on an address subset of the address lines is selected and thus can be read.

[0097] The disclosed fluid-jet printhead die can be used in place of a legacy printhead die that lacks these memory elements but in which the firing mode is still selected via individual assertion of address lines. The disclosed printhead die may include other memory elements that correspond to those of a legacy printhead die and that are selected for reading in a different reading mode. The disclosed printhead die can permit printing devices that use the legacy printhead die to be upgraded to read the disclosed die’s additional memory elements that the legacy die lacks, without having to add or replace hardware within the device.