Title:
ELECTRONIC DEVICE AND NOISE SUPPRESSION METHOD
Document Type and Number:
WIPO Patent Application WO/2013/001692
Kind Code:
A1
Abstract:
A package wiring substrate (300) has a first conductor pattern (14), and a motherboard (13) has a second conductor pattern (15). The second conductor pattern (15) is formed in a region that faces at least part of the first conductor pattern (14), in other words, in a region on which, in a plane view, at least part of the first conductor pattern (14) is overlapped. A repeated conductor structure is formed using either or both of the first conductor pattern (14) and the second conductor pattern (15). The first conductor pattern (14) and the second conductor pattern (15) constitute at least part of an EBG structure (20). The second conductor pattern (15) is electrically connected to another conductor that the motherboard (13) has.
Inventors:
ISHIDA HISASHI (JP)
Application Number:
PCT/JP2012/002526
Publication Date:
January 03, 2013
Filing Date:
April 12, 2012
Export Citation:
Assignee:
NEC CORP (JP)
ISHIDA HISASHI (JP)
ISHIDA HISASHI (JP)
International Classes:
H05K9/00; H01L23/12; H01Q15/14; H05K1/02; H05K1/14
Domestic Patent References:
| WO2009082003A1 | 2009-07-02 |
Foreign References:
| JP2006245193A | 2006-09-14 | |||
| JP2007531253A | 2007-11-01 | |||
| JP2011124503A | 2011-06-23 |
Attorney, Agent or Firm:
HAYAMI, SHINJI (JP)
Shinji Hayami (JP)
Shinji Hayami (JP)
Download PDF:
Claims:
Previous Patent: BUTTON LOCK
Next Patent: SULFUR-CONTAINING POSITIVE ELECTRODE ACTIVE MATERIAL AND METHOD FOR PRODUCING SAME, AND POSITIVE ELE...
Next Patent: SULFUR-CONTAINING POSITIVE ELECTRODE ACTIVE MATERIAL AND METHOD FOR PRODUCING SAME, AND POSITIVE ELE...