Title:
EMULATOR WITH SWITCHING NETWORK CONNECTIONS
Document Type and Number:
WIPO Patent Application WO2002086723
Kind Code:
A3
Abstract:
Serializing and deserializing circuits are provided on an emulator circuit board to group input and output signals of programmable logic devices for routing through a cross point switch. In one instance, the input and output signals of the programmable logic devices are time-multiplexed signals of virtual interconnections. The cross point switch can be configured for static or dynamically scheduled operations.
Inventors:
GOODE TERRY LEE
Application Number:
PCT/US2002/012603
Publication Date:
December 18, 2003
Filing Date:
April 22, 2002
Export Citation:
Assignee:
IKOS SYSTEMS INC (US)
International Classes:
H01L21/82; G06F17/50; (IPC1-7): G06F17/50
Other References:
BURSKY D: "FPGA combines multiple serial interfaces and logic", ELECTRONIC DESIGN, 2 OCT. 2000, PENTON PUBLISHING, USA, vol. 48, no. 20, pages 74 - 76, 78, XP008022566, ISSN: 0013-4872
LI J ET AL: "ROUTABILITY IMPROVEMENT USING DYNAMIC INTERCONNECT ARCHITECTURE", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE INC. NEW YORK, US, vol. 6, no. 3, 1 September 1998 (1998-09-01), pages 498 - 501, XP000782324, ISSN: 1063-8210
BABB J ET AL: "LOGIC EMULATION WITH VIRTUAL WIRES", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE INC. NEW YORK, US, vol. 16, no. 6, 1 June 1997 (1997-06-01), pages 609 - 626, XP000740507, ISSN: 0278-0070
VARGHESE J ET AL: "AN EFFICIENT LOGIC EMULATION SYSTEM", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE INC. NEW YORK, US, vol. 1, no. 2, 1 June 1993 (1993-06-01), pages 171 - 174, XP000390610, ISSN: 1063-8210
See also references of EP 1390850A2
LI J ET AL: "ROUTABILITY IMPROVEMENT USING DYNAMIC INTERCONNECT ARCHITECTURE", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE INC. NEW YORK, US, vol. 6, no. 3, 1 September 1998 (1998-09-01), pages 498 - 501, XP000782324, ISSN: 1063-8210
BABB J ET AL: "LOGIC EMULATION WITH VIRTUAL WIRES", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE INC. NEW YORK, US, vol. 16, no. 6, 1 June 1997 (1997-06-01), pages 609 - 626, XP000740507, ISSN: 0278-0070
VARGHESE J ET AL: "AN EFFICIENT LOGIC EMULATION SYSTEM", IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, IEEE INC. NEW YORK, US, vol. 1, no. 2, 1 June 1993 (1993-06-01), pages 171 - 174, XP000390610, ISSN: 1063-8210
See also references of EP 1390850A2
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