ENERGY EFFICIENT POWER DISTRIBUTION FOR 3D INTEGRATED CIRCUIT STACK

Title:

ENERGY EFFICIENT POWER DISTRIBUTION FOR 3D INTEGRATED CIRCUIT STACK

Document Type and Number:

WIPO Patent Application WO/2012/135772

Kind Code:

A3

Abstract:

Multiple dies can be stacked in what are commonly referred to as three-dimensional modules (or "stacks") with interconnections between the dies, resulting in an IC module with increased circuit component capacity. Such structures can result in lower parasitics for charge transport to different components throughout the various different layers. In some embodiments, the present invention provides efficient power distribution approaches for supplying power to components in the different layers. For example, voltage levels for global supply rails may be increased to reduce required current densities for a given power objective.

Inventors:

SARASWAT RUCHIR (GB)
SCHAEFER ANDRE (DE)
SUPRIYANTO SUPRIYANTO (DE)

Application Number:

PCT/US2012/031705

Publication Date:

March 14, 2013

Filing Date:

March 30, 2012

Export Citation:

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Assignee:

INTEL CORP (US)
SARASWAT RUCHIR (GB)
SCHAEFER ANDRE (DE)
SUPRIYANTO SUPRIYANTO (DE)

International Classes:

G11C5/14; G11C5/02

Foreign References:

US20100290188A1	2010-11-18
US20090103855A1	2009-04-23
US20110050320A1	2011-03-03
US7906853B2	2011-03-15

Other References: