BACKGROUND

State-of-art Clock and Data recovery (CDR) circuits use an analog or digital phase-locked loop (PLL) in combination with a phase detector (PD). Popular choices for PDs are the bang-bang PD or Hogge-PD.

However, in a CDR with a PD the frequency acquisition range is typically quite limited.

Hence, if the initial frequency of the voltage-controlled oscillator (VCO) deviates from the bit rate significantly, the CDR PLL will not achieve phase lock.

More precisely, if the difference between the VCO frequency and the bit rate is significantly larger than the PLL noise bandwidth, the PLL cannot lock reliably.

In many wireline communication standards stringent jitter transfer and jitter tolerance specifications have to be fulfilled which lead to a small loop bandwidth and hence a small locking range of the CDR.

As a consequence, the VCO can only lock if its initial frequency deviation is very small or if additional circuitry for frequency acquisition is used in the CDR PLL.

The state-of-the-art techniques for frequency acquisition are such as phase-frequency-detectors which can operate on data signals, dual-loop PLLs with a frequency-locked loop and external frequency reference, frequency-ramping with lock detection, e.g., as described in "A 9.8-10.7 Gb/s Bang-Bang CDR with Automatic Frequency Acquisition Capability" of the authors Dodel, N., Klar, H., Otte, S. in 2006 49th IEEE International Midwest Symposium on Circuits and Systems,2, 46 - 49, strobe point detector, and others.

Also, in US Patent 8,963,594 82 the offset currents are used to operate the dual-loop PLL in desired linear working range, however not to enhance frequency acquisition.

Problems in prior art The frequency acquisition techniques can increase circuit complexity, require lock detection, and increase power dissipation of the CDR significantly. Some techniques require an additional frequency reference, which could be realized by a quartz oscillator and again increases circuit complexity and power dissipation.

Based on these findings it is an object of the invention to propose a PLL scheme of low complexity which also offers low power consumption while allowing to improve locking properties.

BRIEF DESCRIPTION OF THE FIGURE

The attached figures show

Fig. 1 an overview of main components.

Fig. 2a and 2b exemplary high-level architecture of embodiments according to the invention,

Fig. 3 a prior art implementation.

Fig. 4 an exemplary high-level architecture of embodiments according to the invention,

Fig. 5 shows the implementation of the CP+LF for a differential PLL topology

DETAILED DESCRIPTION

The present disclosure describes preferred embodiments with reference to the Figures, in which like reference signs represent the same or similar elements.

Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.

The described features, structures, or characteristics of the invention may be combined in any suitable manner in one or more embodiments. In the description, numerous specific details are recited to provide a thorough understanding of embodiments of the invention. I.e., unless indicated as alternative only any feature of an embodiment may also be utilized in another embodiment. ln addition, even though at some occurrences certain features will be described with reference to a single entity, such a description is for illustrative purpose only and actual implantations of the invention may also comprise one or more of these entities.

I.e., usage of singular also encompasses plural entities unless indicated.

A CDR PLL comprises three main components (see Fig. 1), namely a phase detector (PD), a charge pump and loop filter (CP+LF), and a voltage-controlled oscillator (VCO).

The phase detector PD is provided with a phase reference signal (data) at a first input Di _n . and provide its recovered data signal at output D _ou t for the CDR application.

The phase detector PD compares the phases of D _in and the (looped back) VCO output to produce UP or DN (down) signals. Based upon the UP or DN signals, the proportional (V _pr op) and integral (Vint) branch control voltages are steered to increase or decrease the VCO phase/frequency.

By means of low-frequency offset current modulation - as provided for by the invention - shown in Fig.2a with appropriately selected modulation parameters the frequency acquisition range of the PLL can be extended greatly, even up to the full tuning range of the voltage-controlled oscillator (VCO).

By means of the offset current modulation the voltage Vint may be modulated and the VCO center frequency may be thereby changed.

As long as the PLL is out of lock with VCO center frequency is away from the acquisition range of the PLL, there are approximately equal numbers of UP pulses and DN pulses.

In this case the average current of the charge pump CP (without offset currents) will be zero.

Hence by adding an offset current to the capacitor C, Vint will change accordingly and the VCO center frequency is modulated. When the VCO center frequency is near enough to the bit rate of D _in or the acquisition range the PLL, it will lock.

In the locked state, the PLL keeps the phase difference between Din and the VCO output signal below one clock period and is able to track the phase difference properly. Hence the charge pump CP current will no longer be zero but determined by the instantaneous phase difference.

If the modulation current (l _O s, _P , los.n.) is selected accordingly, i.e. made sufficiently small enough, the PLL will stay locked while a small modulation of the phase difference will counteract the offset current modulation in order to keep the average of the total charge pump current (including offset current) zero.

Also, the frequency of the modulation current shall be selected accordingly, e.g., low, preferably very low, because this affects the PLL dynamics less in the locked state, which has positive consequences on jitter transfer and jitter tolerance.

In addition, the frequency acquisition range may be enhanced or even maximized for lower modulation frequencies.

Low modulation frequency is good for three reasons: First of all, low modulation frequency will give the PLL more time to lock which is especially good if the input data signal exhibits high noise levels and will increase frequency acquisition range for noisy input signals. Secondly, the modulation frequency must be significantly smaller than PLL bandwidth to allow for maximum frequency acquisition range. Thirdly, typically VCOs have lower tuning sensitivity near maximum and minimum frequency. Slower modulation of offset currents allows for more time for acquisition near the maximum and minimum frequencies of the VCO, thus facilitating locking at such frequencies.

However, sometimes the PLL is required or lock within a specific time, the so-called maximum lock time.

If existent, this maximum lock time requirement sets a lower boundary of the modulation frequency, because the lower the modulation frequencies the longer it takes for the PLL to lock.

Under all these circumstances, the modulation current can be permanently applied to the capacitor C.

This is advantageous, because in case the PLL will lose lock the permanent modulation of the offset current will automatically allow to achieve lock again. In prior art as described above in the article of Dodel, N., et al. an additional loss-of-lock detector is needed to initiate frequency acquisition when the PLL is out of lock which increases circuit complexity and power dissipation.

Furthermore, lock detection circuits typically indicate loss-of-lock with a certain delay, e.g., introduced by a low-pass filter. This causes a delay before the acquisition process can start. With permanent modulation of the offset current the PLL starts the acquisition process immediately without delay.

In the above cited patent offset currents are controlled to set the values of V _prO p and Vint such that the PLL works in the desired linear working range to reduce the spurious tone in a dual-loop PLL but does not provide for frequency acquisition / locking range.

The permanent modulation current can be any periodic waveform including sinusoidal or rectangular or triangular or PWM waveforms.

Using permanent modulation of offset current, Vint can be steered from supply voltage to ground voltage covering the whole tuning range of the VCO.

It also allows to lock the PLL in a very short time, typically less than a millisecond, does not need to wait for the loss of lock detection, does not need any additional high-speed circuitry nor an external reference, and is very power efficient.

Fig.2b shows another way of representing the invention. The scheme operates similar to the above system (cf. Fig. 2a). The charge pump current (l _cp ) may be composed (sum) of proportional (l _C p, _pop ) and integral (Icp nt) currents. Vcti is the control voltage to tune the VCO. The offset currents are injected in the capacitor to set the V _in t.

Fig.3 shows the implementation of the charge pump+loop filter (CP+LF) or transconductance circuit as in the prior art article. The emitter coupled transistor pair Q1-Q2 is biased by a current 2l _cp .int- The PMOS current mirror P1/P3 loads the transistor Cfe. Based upon UP and DN signal from the phase detector PD, the current l _ou t switches between l _C p.i _n t and - Icp.int- The offset or mismatch current l _mm is introduced so that the current sunk or sourced out of the capacitor C can be matched. Also, the or mismatch current lmm is coupled with the state of the phase detector PD. The disadvantage of this is the need of lock detector circuit to enable the loss-of-lock (LOL) switches S1-S2. When the PLL is out of lock, the loss-of-lock detector closes the switch Si for a small time period and the Vint is loaded to VCC. Also, the mismatch current Imm is induced temporarily through closing the switch S2 during the frequency acquisition. This sets the VCO to maximum oscillation frequency. The state of the phase detector PD signals and or mismatch current l _m m leads to the frequency acquisition. The offset current either aids or prevents the frequency acquisition as it is described in the prior art article.

Fig. 4 shows the implementation of the novel circuit.

Based upon UP and DN signals, the transistors Q1-Q2 steer the current Icp nt charge the capacitor C through current mirror P ₃ -P ₄ and discharge it through the current mirrors P1-P2 and N1-N2.

The offset currents l _0S , _P and l _os ,n introduced are independent of the phase detector state.

The output impedances of the P ₄ and N2 form a resistive divider and may be (and most often will be or preferably are) different due to the operating point, temperature variations, process parameter mismatch and PMOS vs NMOS device sizing. Therefore, the control voltage charges the capacitor C towards VCC or discharge towards VEE over time depending on the device parameters and operating conditions of P ₄ and N2, thus leading inevitably to CP leakage.

The offset current can be manually adjusted to set the V _in t to a desired value between VCC and VEE.

This method may require a lock detector as well. However, the offset current has no influence on the PLL stability requirements or PD state.

Alternatively, one could permanently modulate the offset current so that the Vint value charges and discharges periodically in between VCC and VEE values. The permanent offset current modulation only marginally increases the clock phase error in the VCO, the frequency (e.g., 100 Hz-100 kHz) of the modulation is preferably be chosen low such that the locked PLL may easily compensate the offset currents. Fig. 5 shows the implementation of the CP+LF for a differential PLL topology. Based upon UP and DN signals, the transistors Q21-Q24 steer the current l _C p,int to charge the capacitor C through current mirror P3-P4 and discharge it through the current mirrors P1-P2 and N1-N2.

The invention thereby provides in the different embodiments for an enhancement of the frequency acquisition range of the PLL using permanent modulation of the offset current.

The advantages of the invention in a PLL are enhanced frequency acquisition, no circuit complexity or additional frequency acquisition loops or lock detection required, and power dissipation is negligible. Also, no external reference is needed for frequency acquisition.

In other word, within the invention an enhanced PLL circuit having a phase detector section (PD) and Charge pump and Loopfilter section (CP+LF) is proposed.

Within the enhanced PLL circuit the Enhanced PLL circuit provides a steering signal (Vp _rO , V _in t; V _rt i) towards a voltage controlled oscillator (VCO), whereby an output signal generated by the voltage controlled oscillator is compared in the phase detector (PD) with a reference signal (Din) to thereby provide at least one signal (UP, DN) indicative of a deviation towards the Charge pump and Loopfilter section (CP+LF), to thereby enable said steering signal such that the output signal generated by the voltage controlled oscillator (VCO) is kept locked, whereby the Charge pump and Loopfilter section (CP+LF) is provided with a further offset current modulation (l _os , _p , l _os , _n ), whereby the frequency is low with respect to the frequency of the output signal generated by the voltage controlled oscillator.

In embodiments of the invention the frequency of the offset current modulation is lower than the noise bandwidth of the overall PLL circuit.

In still a further embodiment of the invention the circuit is or comprises an integrated circuit.

According to another embodiment of the invention the circuit comprises discrete components.

According to yet another embodiment of the invention the offset current is provided only temporarily. This would further reduce the phase error in the locked state.