Background of the Invention, Prior Art Sacrificial layer technology is of great importance in microengineering. It allows the releasing or lift-off of entire structures or just of some parts of a device that needs to be free-standing.

Sacrificial materials are used as"forms"or"spacers"to make desired shapes and are later removed. In a sense, when photo resist is used to define a pattern, it is a sacrificial layer, since it is almost always removed. However, in the current context, sacrificial processes refer to those which are used for making free-standing or lifted-off structures.

Standard releasing techniques use chemical means to remove a layer by etching it, e. g., by plasma or wet etching techniques. This techniques cab lead to isotropic etching so that lateral under etching of the sacrificial layer depends strongly on its thickness. As those sacrificial layers are

normally in the range of some micrometers, it is very difficult and sometimes even impossible to release large structures.

US-A-5,286,335 discloses a process providing for lifting-off thin film semiconductors having a thickness of typically between 1 and 20 micrometers. An epitaxial layer is deposited on a sacrificial layer (made of aluminium arsenide, AlAs) situated on a growth substrate. After coating the epitaxial layer with a transparent carrier layer, the sacrificial layer is etched away to release the combination of the epitaxial layer and the transparent carrier layer from the growth substrate. Etching is done by using a standard HF: H20 (1: 10) etch solution.

US-A-5,465,009 discloses a similar process where the lift-off is facilitated by patterning the carrier layer with perforations uniformly across an array of devices. Because the maximum distance any sacrificial layer etch must progress laterally during etching of the sacrificial layer is less than the spacing between the devices, the time to release the devices from the growth substrate is much shorter, is constant, and is independent of the size of the array of devices. The described process can be applied to the manipulation of macroscopic pieces of semiconductor having thicknesses ranging from a sub micron through the tens of microns, perhaps to 50 microns or more. Diameters could range from the tens of microns to the hundreds of microns, and could approach or even exceed 1 mm.

However, in most cases, due to the large lateral under etching needed as compared to the thickness of the sacrificial layer, etching times are still very long, leading to the risk of corroding the microstructure to be released. This is especially the case when it's not possible to have

perforations in the device layer. Moreover, due to the difficulty of supplying fresh etch solution to the etching interface, under etching can even be impossible.

For the entire releasing of a device, a possibility is to use a loss of adhesion at the interface between device and substrate, while pulling off the device. However, control of a special adhesion level at an interface is difficult, because adhesion must, on the one hand, be good enough for processing the structure before lift-off, and, on the other hand, still weak enough to enable releasing of the structure. Moreover, specific adhesion control is extremely sensitive to process parameters.

Summary of the Invention It is therefore an object of the present invention to provide a simple method for the release of microstructures from a substrate that avoids the disadvantages of the known processes.

It is still another object of the present invention to provide such a method that enhances the under etching of a microstructure by increasing the etching rate of a sacrificial layer.

Still a further object of the present invention is to provide a method that allows electroetching of the sacrificial layer without the need of an external power supply.

These and other objects and advantages are achieved by the method disclosed in Claim 1.

Preferred embodiments of the invention are described in the dependent claims.

Brief Description of the Drawings Preferred embodiments of the present invention will now be described in more detail hereinafter, by way of example only, in connection with the accompanying drawings, in which: Figs. 1A to 1C schematically show the process steps for making one part of a microstructure free-standing or for completely releasing it from a substrate according to the method of the invention; Figs. 2A to 2C schematically show the same process steps as in Fig. 1A to 1C for a non-flat substrate; Figs. 3A and 3B schematically show the process steps for etching very thin prestructured sacrificial material according to the method according to the invention; Fig. 4 schematically shows the arrangement of a structure in a suitable electrolyte according to the method of the invention; and, Fig. 5 depicts the complete lift-off of a large photo plastic tip array according to the process of the present invention.

Detailed Description of the Preferred Embodiment The present invention seeks to facilitate releasing of microstructures using the enhanced etching rate of a

sacrificial layer via electroetching without requiring an external power supply. The microstructures may consist of microelectronic and/or micro mechanical devices or the like.

In addition, the term"microstructures"is not limited to structures in the micrometer range, but will, in general, indicate very small structures, such as structures in the nanometer range (nanostructures), and the like. However, in the following, the term"microstructures"will be used as a collective term for all these types of structures.

With reference to Figures 1 and 2 in combination, enhanced etching can be used for making one part of the microstructure free-standing or for completely releasing it from a substrate.

Referring to Figure 3, enhanced sacrificial layer etching can also be used to define very thin cavities or channels underneath microstructures by etching very thin prestructured sacrificial material.

In a preferred embodiment of the present invention, a film combination of electrically conducting materials at the interface between a substrate and a device thereon generates an internal battery or galvanic cell that gives a sufficiently high electrochemical potential to significantly enhance chemical etching of a sacrificial layer. This allows a faster and more controlled under etching process even if the areas to be released are very large, i. e., in the centimetre range.

As adhesion is kept strong between the substrate, the sacrificial layer and the microstructure to be released, preferred examples of the present invention allow further robust processing even if relatively high temperature steps or mechanical stress are applied.

To take advantage of the enhanced etching rate of a sacrificial layer by electroetching, a combination of

electrically conducting layers with two different oxido-reduction potentials, forming two electrodes, is employed in preferred embodiments of the present invention.

The electrode with the higher oxido-reduction potential forms the cathode and the electrode having the lower oxido-reduction potential forms the anode.

The electrodes are formed from electrically conducting material such as a conductor or doped semiconductor. However, in an especially preferred embodiment of the present invention, the layers are formed of metals. Preferably, the cathode comprises a noble metal (such as Au, Pd, Pt, Ag, Cu) and the anode comprises a metal selected from a group comprising Al, Zn, Cr, Fe, Co, and the like, or a doped semiconductor.

The anode/cathode oxido-reduction potential difference should be as large as possible to achieve the maximum electroetching efficiency.

The electrically connected layers are immersed into a suitable electrolyte, i. e., a solution or a vapour environment, thus forming a galvanic cell, creating an electrical potential high enough to etch or enhance the etching of the anode. This is shown in Fig. 4. In an particularly preferred embodiment of the present invention, the electrolyte used is an acidic solution known to etch the anode material.

Depending on the chemistry of the materials and the electrolyte used, the electrode potential difference can vary and increases the etch rate of the sacrificial layer or creates a reaction that would normally not occur. In the event that a semiconductor is used for the anode (e. g., Si, SiGe, or GaAs), the electrochemical etching can be enhanced by light generation of electron-holes pairs in the semiconductor.

Etching enhancements of several 100 times higher as compared to chemical wet etching were observed, thus allowing structures of a couple of centimetres to be released successfully.

When such a double layer of conducting material is deposited on a substrate beneath a microstructure to be released, the anodic part of the galvanic cell (the one of the layers having the lower oxido-reduction potential) acts as a sacrificial layer and is etched from the side of the microstructure supporting a fast under etching that leads to rapid release of the microstructure, as illustrated in Fig. 1.

It is noteworthy that the films can be very thin (in the range of about 10 nm) and still produce a very well controlled and fast under etching which is also suitable in thin gap formation. This is useful in situations where structures are not intended to be completely lifted-off, but only a part of the structure is undirected, thus forming a gap between the structure and the substrate.

Another advantage is that substrates do not need to be flat, so that devices fabricated on pre-structured substrates can also be released, as demonstrated in Figs. 2A to 2C.

Such a sacrificial layer technique can also be used for the transfer of structures from any material substrate that is easy to process. It allows releasing of whole devices or only parts thereof of any material.

Figs. 1A to 1C show the process steps according to a method embodying the present invention. First, a substrate 2 is provided. This substrate may consist of a suitable material like, e. g., Si, glass, quartz, ceramics, plastic, and the

like. The substrate need not be flat but can have any shape.

In the next step, two layers 4 and 6 of conducting materials are deposited on said substrate. One of the layers consists of a material having a high oxido-reduction potential, such as a noble metal like Au, Pd, Pt, Ag, Cu, etc. This layer 4 will, in the following, act as a cathode.

The second layer 6 consists of a material having a lower oxido-reduction potential than layer 4, such as, e. g., Al, Zn, Cr, Fe, Co, and the like. This second layer will, in the following, act as an anode. The deposition of the two layers has to be performed in such a way that an electrical contact is present between them.

In a preferred embodiment of the present invention, the cathode is deposited first, and the anode, which will then act as the sacrificial layer, is subsequently deposited on top of the anode, so that the cathode is not released with the lifted part of the microstructure.

After having deposited the two electrodes on the substrate 2, the microstructure 8 to be released is formed on top of this structure by standard deposition and structuring techniques of the materials composing the desired structure (Fig. 1A).

Subsequently, said second layer 6 will be etched electrochemically when immersing this structure 10 into a suitable electrolyte 12 as shown in Fig. 4. The electrolyte 12 may consist of a solution or vapour environment. Thus, a galvanic cell is formed, creating an electrical potential high enough so that the etching of the anode, which acts as a sacrificial layer, occurs or is drastically enhanced.

Fig. 1B shows the final product after only a part of the microstructure 8 has been released from the substrate, whereas Fig. 1C shows release of the complete microstructure 8.

Figs. 2A to 2C schematically depict the same process steps for a non-flat substrate 2.

The process shown in Figs. 1 and 2 can also be used to define very thin cavities or channels underneath microstructures by etching very thin prestructured sacrificial material, as is shown in Figs. 3A and 3B. The sacrificial material is first structured to define the part that need to be released. Thus, micro channels 14 and gaps 16 of a controlled size may be manufactured. It will be appreciated that embodiments of the present invention are particularly although not exclusively useful for fabrication of mechanical oscillators, micro switches, cantilevers, microfluidic channels, micro actuators, suspended coils for RF electronic circuits, and like devices.

The present invention can be used in many releasing processes with micro electromechanical structures (MEMS), integrated optics, or in microelectronic fields. Fig. 5, e. g., shows the complete release of a large photo plastic tip array of 1.6 x 6 mm).

When used with a flip-chip process, examples of the present invention allow integration of any kind of micro fabricated structures or devices onto other microstructures or micro devices, even if their technology is not compatible (MEMS, integrated optics, CMOS, III-V, Si-Ge, etc.). In integrated optics, e. g., the merge of different devices from different technologies on different substrates may be possible (wave guides, mirrors, deflectors, detectors, micro lenses, laser diodes, and the like).

One possible application of the present invention is to integrate cantilevers on a CMOS chip. Building a cantilever on a CMOS chip (post CMOS) is really limiting the processes that can be used for the MEMS part, adding also some yield issue. A simple process would be to fabricate CMOS circuitry and MEMS part separately. The whole cantilevers array could then be released and"flipped"at the end onto the CMOS chip. In this case, a well controlled lift-off of the levers is desirable.

Therefore, preferred embodiments of the present invention are especially suitable for this process.

Epoxy-based Scanning Near-Field Optical Microscopy (SNOM) probes have been fabricated in a photosensitive epoxy resist.

A pyramidal mould etched previously in silicon is used to formed the tip. Once the epoxy probe is fabricated, an optical fibre is introduced in a guiding structure and glued. The whole structure is then lifted-off from the substrate. This is possible by etching a sacrificial layer. In this case, an interface made of a Au layer, a Cr layer, a TaO layer, and a 100 nm thick Al layer was designed. The Al layer is used as optical coating for the SNOM tip, to avoid optical losses of the light down to the tip apex. The Cr-Au layers form the galvanic cell with Cr as an anode that will be etch away. The TaO layer is a dielectric film that electrically isolate the Al film in order to prevent the formation of a second galvanic cell (made with the Au film and the Al film) which, in this case, would otherwise lead to the unwanted etching of the Al.