EQUIPHASE POLYPHASE CLOCK SIGNAL GENERATOR CIRCUIT AND SERIAL DIGITAL DATA RECEIVER CIRCUIT USING THE SAME

Title:

EQUIPHASE POLYPHASE CLOCK SIGNAL GENERATOR CIRCUIT AND SERIAL DIGITAL DATA RECEIVER CIRCUIT USING THE SAME

Document Type and Number:

WIPO Patent Application WO/2005/109642

Kind Code:

A1

Abstract:

[PROBLEMS] To realize a circuit capable of keeping the duty ratio of the output equiphase polyphase clock signal constant independently of the duty ratio of an input signal, while minimizing an increase of the number of elements and further suppressing an increase of the circuit area of the semiconductor board and an increase of the power consumption. [MEANS FOR SOLVING PROBLEMS] In the equiphase polyphase clock signal generator circuit, an input clock signal is frequency divided by two, thereby converting it to a complementary clock signal, which is then inputted to a complementary voltage control delay element array. Since the input clock signal has been frequency divided by two, the complementary clock signal as frequency divided is not dependent on the duty ratio of the input clock but holds a constant duty ratio. This complementary clock signal as frequency divided is inputted to the voltage control delay element array, a complementary output signal from which is phase compared with the complementary clock signal as frequency divided, whereby an equiphase polyphase clock signal synchronized with the input clock signal can be outputted.

Inventors:

OKAMURA JUN-ICHI (JP)

Application Number:

PCT/JP2005/006647

Publication Date:

November 17, 2005

Filing Date:

April 05, 2005

Export Citation:

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Assignee:

THINE ELECTRONICS INC (JP)
OKAMURA JUN-ICHI (JP)

International Classes:

H03K5/00; H03K5/15; H03L7/081; H03L7/089; H03K5/135; (IPC1-7): H03K5/00; H03K5/15; H03L7/081

Foreign References:

JP2000059183A	2000-02-25
JPH11205102A	1999-07-30

Other References: