Field of the Invention

This invention relates to the fabrication of capacitors, and particularly, but not exclusively, to surface mount capacitors for use in microelectronics applications. The invention also relates to aspects of plasma polymerisation.

Background of the Invention

Surface mount capacitors most usually are constructed as a rectangularly cross- sectioned elongate structure comprising interdigitated plate-like electrodes interposed by a dielectric material. The electrodes each are fixed to one of a pair of terminals, and the capacitor is placed in circuit by fixing the terminals to lands on a printed circuit board by means such as soldering, gluing with a conductive adhesive or wire bonding. In microelectronics applications, it is a requirement that surface mount capacitors be as thin as possible in order not to occupy too great a volume on a printed circuit board. For a capacitor of the noted constmction, the capacitance is (approximately) directly proportional to the relative dielectric constant of the dielectric material and to the area of the plate electrodes, whilst it is inversely proportional to the distance between the electrodes. In order to obtain relatively high values of capacitance, yet realise a capacitor of a miniaturised nature, it is common to utilise dielectric materials having a high dielectric constant, and to increase the surface area of the plate electrodes and/or decrease the electrode separation. Often the application also will dictate that the capacitor must be flexible to resist failure through bending.

Many dielectric materials are known - ceramic materials (eg. barium titanate, lead calcium titanate, etc.) having a relative dielectric constant in the range of 10*-- to IO*- ¹ are commonly in use in the fabrication of surface mount capacitors. A subset of these materials, the so-called Negative Positive zerO (NPO) dielectrics, have a relative dielectric constant of about 10-% and are stable over a wide range of temperatures. Nevertheless, it is presently only possible to fabricate and handle a thin film of such NPO dielectric material to a minimum thickness of about 6 to 7 μm.

Recently, there have been advances which have permitted the laying down of thin ceramic films by plasma deposition in a near vacuum. These films are fragile and can fracture when bent, resulting in failure of the capacitor.

Known plastics materials, such as polyethylenes, have a relative dielectric constant in the range of 2 to 5. They exhibit a thermal stability characteristic which is superior to ceramic dielectrics, and have the added advantage of being able to resist impact and bending. This attribute is most desirable where surface mount capacitors are incorporated into devices that are exposed to rough handling, such as RFID devices

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("bag tag"), smart card devices, PCMCIA cards and remote controllers for consumer electronics appliances. In order to utilise such materials in surface mount capacitors, and still achieve a capacitance value comparable to the NPO dielectrics, it is necessary to increase the surface area of the plate electrodes or, more importantly, to decrease the separation between the plate electrodes.

Thin film dielectric materials have the tendency not to be uniform, resulting in 'pin-holes' in their surface. These pin-holes inevitably lead to failure of capacitors constructed from the thin film dielectric material. It is thus important that the method of fabrication be able to lay-down a near-perfect thin film dielectric material. Dielectric materials of any given thickness can withstand only a limited applied potential difference before catastrophic breakdown occurs. In most microelectronics applications, the maximum potential difference is about 20 V. For plastics materials such as polyethylenes, having a voltage withstand rating of 600 V/μm, this dictates a minimum thickness in microelectronics applications of about 1/30 μm. Even with a minimum thickness of this order, plastics materials still more than out-perform NPO dielectrics for the same given plate electrode surface area, in that the approximately 50 times lower dielectric constant is more than compensated by a 180 times reduction in thickness.

It is well known that plastics films yield these properties when applied to capacitors as dielectric materials. Further, it is well known that thin contiguous films can be laid down in a vacuum using techmques such as plasma deposition of monomers to form a range of polymers on a substrate. There remains, however, the problem of how these processes can be harnessed for the mass production of capacitors.

Prior art methods (see US Patent Nos. 4599678, 4618507, 4938995, 5035917, German Laid Open Documents (Offenlegungsschrift) 3531578 and 3439688, and Japanese 1-174504) also are known, but fail to address the problems of continuous production of structures requiring two or more metal layers.

Disclosure of the Invention An object of the present invention, therefore, is to provide a fabrication process, amenable to mass production, for thin capacitors that can utilise low relative dielectric constant materials and yet achieve useable capacitance values.

It is a further preferred object of the invention to provide a method that, in the mass production of capacitors, achieves a high uniformity and repeatability of capacitance values, and incorporates a standard fabrication technique for capacitors of all capacitance values. Further, the required capacitance is to be easily selectable.

Therefore, the invention discloses a method of fabricating a capacitor precursor or capacitors, the method comprising the steps of:

depositing a first metal strip continuously along a length of a moving web by passing metal particles through a first mask and onto an area of the web; depositing a dielectric polymer layer continuously over a length of the moving web and over at least a portion of the first metal strip, the dielectric layer being the product of a low temperature plasma polymerisation; and depositing a second offset metal strip continuously over at least a portion of the first metal strip and the dielectric layer, by passing metal particles through the first or a second mask.

The invention further discloses a method of fabricating capacitors, the method comprising the steps of: laying-down alternating layers of dielectric material and electrode-forming spaced-apart metal strips in a stacked arrangement in a manner such that, in the direction of stacking, the electrode strips in adjacent layers are offset and the electrode strips in alternate layers are in alignment; cutting one or more segments from the stacked arrangement, the or each segment spanning one electrode strip in the aligned stacking; applying a terminal-forming conductive plate to each of two opposed sides of the or each segment, each terminal plate forming an electrical connection with a respective end of alternate electrode strips; and slicing the or each segment transversely along its longitudinal axis to form a capacitor.

Preferably, the step of depositing includes the steps of passing a substrate- forming transport layer past a metal deposition station, the metal deposition station including a slitted screen or mask through which metal is deposited onto the transport layer as a layer of electrode strips; passing the transport layer past a dielectric deposition station for deposition of a dielectric layer; and repeating the metal deposition and dielectric deposition steps until the requisite number of layers has been built up.

There also can be the further step of moving the slitted screen or mask between alternate passes to effect the offset between adjacent metal layers. The invention further discloses apparatus for the fabrication of capacitors, the apparatus comprising: a continuous transport film carried between reversing drums; one or more metallisation stations, each having a slitted grid through which metal is deposited onto the transport film as spaced-apart electrode forming strips as the transport film passes the station; one or more dielectric deposition stations depositing a layer of dielectric material onto the passing transport film;

whereby, with passing of the transport film alternately past a metallisation station and a dielectric deposition station, alternating layers of metal strips and dielectric material are laid-down in a stacked arrangement in a manner such that, in the direction of stacking, the electrode strips in adjacent layers are offset and the electrode strips in alternate layers are in alignment.

The invention yet further discloses a capacitor fabricated in accordance with the above-described method.

The invention yet further discloses a capacitor comprising a structure having alternating layers of plasma polymerised dielectric and metal, the structure having opposite side edges, each side edge exposing only alternate metal layers and not adjacent metal layers, the structure having been sub-divided from an elongated web.

The invention yet further discloses a capacitor precursor comprising an elongated ribbon-like structure having alternating layers of plasma polymerised dielectric and metal, the structure having opposite side edges, each side edge exposing only alternate metal layers and not adjacent metal layers.

Brief Description of the Drawings

Preferred embodiments of the invention now will be described with reference to the accompanying drawings, in which: Fig. 1 is a schematic cross sectional diagram of a reactor vessel sub-divided into three chambers.

Fig. 2 is a schematic representation of processing steps in the fabrication of an intermediate form of a surface mount capacitor;

Fig. 3 shows an alternative process in fabrication of the intermediate form; Fig. 4 is a schematic diagram showing the intermediate form;

Fig. 5 is a schematic representation of further processing steps in the fabrication of the surface mount capacitors; and

Fig. 6 shows finished capacitors.

Best Mode and Other Embodiments of the Invention

Embodiments of me present invention involve methods of manufacture of capacitors, manufacturing devices for practising those methods and capacitors and precursor materials which are formed by those methods and devices. "Precursor" in this context refers to structures which are formed by the methods and devices taught here, but which are not per se individual capacitors in a commercial sense. Even though the precursors are not vendible as individual capacitors, they are considered commercially important in that they may be conveniently converted into individual capacitors. Some of the potential benefits of the invention are precisely that (a) a single

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precursor may be converted into many capacitors having different values, (b) the precursor may be converted into many capacitors of a given value with more accuracy and precision than other methods, and (c) conversion of the precursors into individual capacitors can accommodate or compensate for irregularities which may find their way into the fabrication process so that higher yields may be obtained.

It will be understood that capacitors consist of alternating layers of conductive and dielectric materials. In the case of the present invention, the dielectric materials are formed using low temperamre plasma polymerisation. The metal electrodes are formed using magnetron sputtering equipment, but other metal or metal vapour deposition processes are known and considered suitable. In this disclosure it will be illustrated how these techniques may be applied both in a batch process within a single vessel and in a continuous forming or moving web environment.

Fig. 1 illustrates a single reaction vessel 100 which is sub-divided into three chambers 101, 102 and 103. A single vacuum inlet is capable of evacuating the entire vessel, eg all three chambers. The lower chamber 101 houses a transport or moving carriage 104 which transports a substrate or a capacitor precursor (capacitor in the making) back and forth beneath the two upper chambers. The carriage 104 is made from brass, is electrically grounded and is selectively and accurately reciprocated along a track by a toothed neoprene belt 105 driven by a DC stepping motor 106. One of the upper chambers 103 houses the upper or live RF electrode 107 of d e plasma polymerisation electrode pair and also contains an inlet for the monomer vapour. The other upper chamber 102 houses the magnetron and the metal target 108 which are used in sputtering the metal which forms the electrodes of the capacitor or precursor material. The upper chambers are separated from the lower chamber by a plenum 109. This plenum incoφorates the masks 110, 111 which control the deposition pattern for the dielectric and metallic layers. This plenum also conveniently incoφorates a test station 112 which can be brought to bear onto the substrate or precursor(s) or capacitor(s) held by the carriage so that capacitance measurements can be made in situ. The plenum and divider 114 are raised and lowered by an adjusting screw 113 which is incoφorated into the top plate 115. Locating pins 116 keep the plenum in alignment. This allows the gap between the carriage 104 and the masks 110, 111 and testing station 112 to be adjusted.

A reactor vessel shell 117 has been fabricated from a Pyrex (TM) glass cylinder having an inside diameter of 285mm, a height of 280mm and a wall thickness of 9mm. The top and bottom plates 115, 118 are formed from ultra high molecular weight polyethylene and are positioned by fliree steel rods 119.

The brass carriage 104 is electrically grounded and so completes the RF plasma polymerisation circuit. The carriage is a convenience which permits positiomng

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of the substrate from one location to another. The carriage is adapted to transport a single sheet of substrate. The carriage may also be adapted to transport a moving web from one location to another. A heater 120 is optionally built into the carriage.

The vessel is evacuated using a turbomolecular pump backed by a rotary pump. A neoprene rubber O-ring 121 set in a groove seals the top and bottom plate against the cylinder. Pressure in the range of 100-0.01 torr are measured by a capacitance diaphragm gauge attached to the tube connecting the base plate of the reactor and the turbomolecular pump. Below 0.01 torr, pressure is measured by a cold cathode ionisation gauge attached to the argon inlet. Suitable operating pressures are about 0.1-0.001 torr for the metal deposition steps and about 0.1-1.5 torr for the polymer dielectric deposition steps.

Utilising this type of apparatus it is possible to deposit useful dielectric in thicknesses of about 140nm or more. A capacitance of about 2nF per layer will be obtained from an 160nm thickness dielectric, this providing a good basis for a multi- layer structure.

It will be appreciated that the metal strips or tracks (for example items 12 in Fig. 2) in adjacent metal layers must be laterally offset from one another. Similarly metal strips in alternate metal layers are to be in alignment. These features ensure (a) that the outside edges of each strip are more or less aligned for fabrication puφoses, and (b) that only alternate metal layers are exposed to or extend to any one side of the ribbon or ribbon-like structure from which individual capacitors are eventually separated (see Figs. 4 and 5). To this end, die carriage 104 is capable of transporting the substrate or web to two different laterally separated positions under the metal deposition mask 111. In me alternative, the carriage may transport to a single position at that location, with the mask translating from one alignment to another laterally spaced alignment on alternate metal depositing operations.

Each ribbon or "web" or precursor may consist of one or more discrete parallel rows of alternating metal and dielectric layers formed along the length of the web. A direction along this length is referred to as the machine direction. Transverse to this direction may be referred to as the cross direction. Each row, after machine direction slitting from the web as required, is capable of being sub-divided transversely (cross direction) into individual capacitors of any length or value, in very exact and repeatable increments. The description relating to Figs. 2-6 concerns a continuous production memod. Continuous methods should be considered in the light of die teachings provided here regarding batch production.

From Fig. 2, it can be seen mat the initial processing steps comprise the laying-down of alternating layers of dielectric material and metal strips 12 in a stacked arrangement. Step 1 lays-down a first layer 11 of dielectric material onto a substrate

(not shown) constructed of an inert material such as highly polished stainless steel that may be coated with a release agent. The substrate may also be a polymer film. Kapton™ polyimide film is suggested. Films or webs of Kapton™ in a thickness of about 75um have been demonstrated to be effective. A preferred method of laying-down the dielectric material is in accordance with the process called "plasma polymerisation" and more particularly "low temperamre plasma polymerisation". This process is the subject of a US Patent No. 5449383 now assigned to Commonwealth Scientific and Industrial Research Organisation, and the contents of this application is incoφorated herein by cross-reference. Reference may also be made to an article entitled Plasma Polymerisation. Vacuum (1989) volume 39, p.421. A RF power source is used. Microwave or AC power sources may also be used. The first layer of dielectric material is of a predetermined thickness. Suitable monomers are perfluorocarbons, aliphatic and aliphatic hydrocarbons, silanes and siloxanes. A preferred monomer is hexamethyldisiloxane (HMDSO). Step 2 lays-down a first layer of spaced-apart metal strips 12 that ultimately form the electrodes of a capacitor. The process utilised in laying down the strips of metal preferably can be either plasma deposition (sputtering) or a metal vapour technique. The metal may include platinum, palladium, nickel, copper or aluminium. Platinum has been demonstrated as effective. Both these processes allow fine control over the thickness of the dielectric material and metal layers or strips respectively, and with particular reference to the laying-down of die dielectric material. These processes assure a dielectric material free of pin-holes.

These same two steps are repeated, thus building up a stacked structure that can be hundreds of layers tiiick. A rotating turntable arrangement conveniently can be used. The layers of dielectric material 11,13,15,17 occupy the interstices between the metal strips 12,14,16 thus fully enveloping the metal strip electrodes. The metal strips 12,14,16 of adjacent layers are laid-down in a manner to be partially offset with respect to each other, but also arranged so that the electrodes of alternate metal strip layers are precisely aligned. This arrangement is for a reason that will become apparent.

Fig. 3 shows apparatus for effecting an alternative method in the fabrication of an intermediate form or precursor of a surface mount capacitor. The apparams comprises reversing drum reels 20,21 carrying a continuous transport film 22 acting as a substrate. The transport film 22 may be a plastics material such as Kapton™, in which case it is liable to remain with the resultant capacitors for their lifetime. As an alternative, a thin stainless steel film can be used, which might be 'peeled away' from the resultant capacitor laminate structore. The film 22 passes by three stages, two of

which relate to metallisation in the laying-down of the strip electrodes, with the other relating to polymerisation and the laying-down of the dielectric material.

The plastics film 22 dierefore passes a guide reel 23 and around substantially the whole circumference of a process drum 24 (cooled if required), at which point the transport substrate, film or web 22 comes under the influence of a vacuum metallisation source 25. Metal is deposited onto the transport film 22 passing through a slitted screen or mask 26. The slits are configured to be longitudinal of the transport film. Where there are openings in the screen 26, the metal will be laid onto the transport film 22, thus forming the electrode strips, such as are shown in Fig. 2. The transport film 22 exits the process drum 24 by another guide reel 27, and so proceeds to a further process drum 28.

Here, the transport film is subjected to a vacuum monomer source 29, thus with passage of the film, lays down a layer of dielectric material. The film 22 then passes to a yet further guide reel 30, and then to another cooled process drum 31 that relates to a further metallisation source 32 and associated screen or mask 33. Thus a further layer of metallisation is laid down as electrode strips, and is borne off d e process drum 31 by a further guide reel 34. The respective screens 26,33 are arranged so that adjacent layers of strip electrodes are offset in d e manner shown in Fig. 2. At this point, the transport film 22 is reversed past the metallisation process drum 31 without a further layer of metal being laid-down, and so back to the polymerisation process drum 28, where a further layer of dielectric material is laid down and again passing to the first metallisation process drum 24. By having two metallisation process drums 24,31, it is possible to use static screens 26,33 and still achieve me relative offset between adjacent layers of electrodes and precise alignment between alternate layers of electrodes.

It may also be necessary to periodically clean the slitted screens 26,33 to avoid 'blurring' of the laid-down metal strips due to a build-up of metal on the slits of the screens memselves. For this reason the slitted screens 26,33 may be moving/reversing on reels (much in the nature of a typewriter ribbon) and continuously cleaned at a cleaning station. As an alternative to a cleaning station, the moving screens can be disposable after one or more usages.

It is further equally possible only to have a single metallisation stage, in which case the screen must be adjustable (movable) to obtain the relative offsets.

Fig. 4 shows a stacked arrangement representing an intermediate form 10 of a capacitor. The intermediate stacked arrangement conveniently is shown as nine layers of electrode strips, each adjacent layer separated by a dielectric layer. The metal and dielectric layers are of a uniform and consistently reproducible thickness. The vertical lines indicate the point of cutting along the longitudinal extent of d e stacked assembly

to form segments. The cutting points dierefore preferably coincide with end portions of the metal strips in alternate layers. The cutting step can be achieved by use of a conventional precision splitter or guillotine. The material occurring outside of the dimension X is waste. This form of slitting has the effect of exposing or revealing the side edges of the metal electrodes. The individual edges are later electrically connected as will be explained. In the alternative, the polymer dielectric can be masked from the side edges of the metal layers so mat alternate but not adjacent metal layers form in direct contact.

Fig. 5 shows one segment 40 cut from the intermediate arrangement of Fig. 4 (albeit at a different scale to Fig. 4). The segment 40 forms a series of interdigitated metal electrodes 41-54, alternate ones of which are exposed at a common edge. The electrodes 41-47 are commonly connected to a metal terminal plate 55 at the left-hand edge, thereby commonly electrically connecting those alternate plate electrodes. The odier electrodes 48-54 similarly are connected to another metal terminal plate 56 at the right-hand edge. 'Connection' of the terminal plates can be achieved by dipping die respective segment edges into a conductive solution to achieve a coating by electroless plating or by a further metallisation process.

The separation between adjacent plate electrodes and the relative dielectric constant therefore are fixed. The fabrication process is arranged such that the dimension X represents the length of the capacitor to suit each particular industry standard package size. Laying down a large number of thin film layers such that all the dimensions are precisely known is difficult to achieve repeatably. In order to overcome this problem, a further processing step is taken to form a number of individual capacitors from the segment 40 shown in Fig. 5. The segment 40 is sliced in a plane transverse to its longitudinal axis (dimension Z) to achieve a desired surface area (Z x X) , thus manipulating d e capacitance of the resultant capacitor, in accordance with the considerations discussed above.

The end face margins of the segments 40 must be cropped before d e slicing process takes place, as the exposed interdigitated electrodes will all be short-circuited by a metal layer built-up in the course of forming the terminals 55,56.

The position of the slices can be determined by calculation - that being a reflection of die selected surface area for each plate electrode, else can be obtained by trial slices to obtain a number of resulting capacitors of varying surface area. These capacitors can be measured for their capacitance value, and because of the high uniformity and reproducibility of the memod, capacitors of a highly predictable capacitance value can be produced simply by reproducing that slicing position. As such, the process is particularly suited to automated mass production.

Fig. 6 shows finished surface mount capacitors 60 that result from a final processing stage of removing metal smears resulting from the slicing procedure, by a light metal etching procedure. The capacitors 60 may be packaged as required by a particular application, and are men ready for use.

Statement of Industrial Applicability

The invention can provide me capacitor-making industry wid a variety of new methods, including continuous methods, and devices for fabricating a new type of capacitor. The capacitor taught by the specification has applications in surface mount circuitry and in environments where temperature stability, thickness or price may be a consideration.