Title:
FAILED BIT REPAIR METHOD, DEVICE AND APPARATUS, AND STORAGE MEDIUM
Document Type and Number:
WIPO Patent Application WO/2022/095512
Kind Code:
A1
Abstract:
A failed bit repair method, device and apparatus, and a storage medium, relating to the technical field of semiconductors. The method comprises: acquiring repair specifications of a backup circuit for a chip in which a failed bit is located (S202); standardizing the repair specifications of the backup circuit, so as to obtain standardized repair specifications (S204); acquiring the location of the failed bit on the chip (S206); processing the location of the failed bit on the chip according to the standardized repair specifications, so as to obtain a standardized location of the failed bit (S208); using a backup circuit allocation algorithm to allocate the backup circuit according to the standardized location of the failed bit and the standardized repair specifications, so as to obtain a standardized repair location of the backup circuit (S210); and using, according to the standardized repair specifications, the standardized repair location of the backup circuit as a repair location of the backup circuit on the chip, and repairing the failed bit (S212). The method improves the range of applications of repair algorithms.
Inventors:
CHEN YUI-LANG (CN)
Application Number:
PCT/CN2021/108195
Publication Date:
May 12, 2022
Filing Date:
July 23, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G06F30/398
Foreign References:
| CN101765889A | 2010-06-30 | |||
| CN107437435A | 2017-12-05 | |||
| CN110879931A | 2020-03-13 | |||
| US20200097842A1 | 2020-03-26 |
Other References:
WANG FAN: "The Restorative Procedure of Non-Uniform Distribution Redundancy in DRAM", SCIENCE AND TECHNOLOGY & INNOVATION, CN, no. 9, 30 September 2017 (2017-09-30), CN , pages 130 - 131, XP055928565, ISSN: 2095-6835, DOI: 10.15913/j.cnki.kjycx.2017.09.130
YU YONGJIAN, QIAOYUN ZOU, DONG LV, JIAN LU: "Application of Collaborative Analysis in Failure Location of Integrated Circuits ", ELECTRONICS & PACKAGING, vol. 17, no. 172, 31 August 2017 (2017-08-31), XP055928570, ISSN: 1681-1070, DOI: 10.16257/j.cnki.1681-1070.2017.0101
YU YONGJIAN, QIAOYUN ZOU, DONG LV, JIAN LU: "Application of Collaborative Analysis in Failure Location of Integrated Circuits ", ELECTRONICS & PACKAGING, vol. 17, no. 172, 31 August 2017 (2017-08-31), XP055928570, ISSN: 1681-1070, DOI: 10.16257/j.cnki.1681-1070.2017.0101
Attorney, Agent or Firm:
BEIJING INTELLEGAL INTELLECTUAL PROPERTY AGENT LTD. (CN)
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