Title:
FAILURE DETERMINATION CIRCUIT, IMAGE CAPTURING DEVICE, AND VOLTAGE DETECTION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2024/101076
Kind Code:
A1
Abstract:
A failure determination circuit according to one embodiment of the present disclosure comprises: a charge pump circuit that includes an amplification section having an output section capable of outputting a first voltage, and a switch section, and that is capable of generating a second voltage based on the first voltage; a detection section that is electrically connected to the output section of the amplification section, and is capable of outputting a first signal according to the first voltage output from the output section; and a determination section capable of executing a failure determination on the basis of the first signal.
Inventors:
MIYAZAKO TAMON (JP)
Application Number:
PCT/JP2023/037335
Publication Date:
May 16, 2024
Filing Date:
October 16, 2023
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H02M3/07; H01L27/144; H01L27/146; H03K17/00; H03K17/06; H04N25/00
Domestic Patent References:
| WO2022207368A1 | 2022-10-06 | |||
| WO2017086042A1 | 2017-05-26 |
Foreign References:
| JP2003023770A | 2003-01-24 | |||
| JP2021010298A | 2021-01-28 | |||
| JP2009124931A | 2009-06-04 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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