Title:
FEC DRIVEN LINK OPTIMIZATION
Document Type and Number:
WIPO Patent Application WO/2019/015483
Kind Code:
A1
Abstract:
Methods, systems and computer-readable media for optimizing SerDes system parameters based on a bit error rate detected by a forward error correction unit (FEC). A SerDes receiver receives a data stream over a link and uses a (FEC) to detect error information in the received data stream. The system tunes and optimizes one or more SerDes system parameters using the detected error information. The system minimizes power consumption by decreasing power supply voltage until a maximum acceptable input error rate threshold is reached. The (FEC) allows the system to tolerate errors in the input data stream up to the threshold while preventing propagation of these errors in the (FEC) output data stream.
Inventors:
TONIETTO DAVIDE (CA)
LACROIX MARC-ANDRE (CA)
WONG HENRY (US)
LACROIX MARC-ANDRE (CA)
WONG HENRY (US)
Application Number:
PCT/CN2018/094688
Publication Date:
January 24, 2019
Filing Date:
July 05, 2018
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H03M13/03; G06F11/07
Foreign References:
| US20140108879A1 | 2014-04-17 | |||
| US20090187807A1 | 2009-07-23 | |||
| CN101057458A | 2007-10-17 |
Download PDF:
Previous Patent: TERMINAL AND VIEW CHARACTER COPYING METHOD THEREOF, AND STORAGE APPARATUS
Next Patent: OPTICAL MODULE AND NETWORK DEVICE
Next Patent: OPTICAL MODULE AND NETWORK DEVICE