Title:
FEC FRAME PROCESSING DEVICE AND FEC FRAME PROCESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2015/133288
Kind Code:
A1
Abstract:
A Forward Error Correction (FEC) frame processing device, wherein the FEC frame processing device is provided with: a frame configuration control unit for determining a frame configuration by notifying the number of Optical-channel Data Tributary Unit (ODTU) tributary slots for accommodating a client signal; an encoding unit for configuring, on the basis of the frame configuration, the number of columns in an encoding matrix with N times or 1/N times the length of an Optical Transport Network (OTN) frame (where N is an integer greater than or equal to 1), the encoding unit being capable of increasing or reducing the number of rows in the encoding matrix in units of ODTU tributary slots; and a decoding unit for configuring, on the basis of the frame configuration, the number of columns in an inspection matrix with N times or 1/N times the length of the OTN frame, the decoding unit being capable of increasing or reducing the number of rows in the inspection matrix in units of ODTU tributary slots.
Inventors:
KAMETANI SOICHIRO (JP)
KUBO KAZUO (JP)
KUBO KAZUO (JP)
Application Number:
PCT/JP2015/054587
Publication Date:
September 11, 2015
Filing Date:
February 19, 2015
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H04L1/00; H03M13/19; H03M13/35; H04J3/00
Domestic Patent References:
| WO2013084341A1 | 2013-06-13 | |||
| WO2011062111A1 | 2011-05-26 |
Foreign References:
| JP2011109228A | 2011-06-02 |
Other References:
KEN'YA SUGIHARA ET AL.: "Coding Rate Adjustment for LDPC Codes by Row-Splitting", 2010 NEN THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS SOGO TAIKAI KOEN RONBUNSHU KISO.KYOKAI, March 2010 (2010-03-01), pages 123
Attorney, Agent or Firm:
SOGA, Michiharu et al. (JP)
Michiharu Soga (JP)
Michiharu Soga (JP)
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