Title:
FERROELECTRIC MEMORY
Document Type and Number:
WIPO Patent Application WO2003096352
Kind Code:
A3
Abstract:
A ferroelectric memory (436) including a bit line pair (102, 104), a drive line (103) parallel to and located between the bit lines, and an associated memory cell (100). The memory cell includes two ferroelectric capacitors (106, 108), each capacitor connected to one of said bit lines via a transistor (105, 109), and each capacitor also connected to the drive line via a transistor (107). The gates (123, 136, 128) of all three of the transistors are connected to a word line (101) perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. A sense amplifier (502) with three bit line inputs (519, 516, 518) compares the cell bit line with a signal derived from the two dummy bit lines (226, 228). The memory cells are read with a non-destructive read out method that differentiates between the different capacitances of a ferroelectric capacitor in different ferroelectric polarization states.
Inventors:
HO IU-MENG TOM (US)
Application Number:
PCT/US2003/014015
Publication Date:
June 24, 2004
Filing Date:
May 05, 2003
Export Citation:
Assignee:
SYMETRIX CORP (US)
IOTA TECHNOLOGY INC (US)
HO IU-MENG TOM (US)
IOTA TECHNOLOGY INC (US)
HO IU-MENG TOM (US)
International Classes:
G11C11/22; H01L21/8246; H01L27/105; (IPC1-7): G11C11/22
Foreign References:
| EP0938096A2 | 1999-08-25 | |||
| EP0278167A2 | 1988-08-17 | |||
| DE19963417A1 | 2000-07-20 | |||
| US5737260A | 1998-04-07 | |||
| EP0757354A2 | 1997-02-05 | |||
| EP0759620A2 | 1997-02-26 | |||
| US5828615A | 1998-10-27 | |||
| EP0829882A1 | 1998-03-18 |
Other References:
See also references of EP 1502265A2
Download PDF:
Previous Patent: MEMORIES AND MEMORY CIRCUITS
Next Patent: SURFACE-SMOOTHING CONDUCTIVE LAYER FOR SEMICONDUCTOR DEVICES WITH MAGNETIC MATERIAL LAYERS
Next Patent: SURFACE-SMOOTHING CONDUCTIVE LAYER FOR SEMICONDUCTOR DEVICES WITH MAGNETIC MATERIAL LAYERS