This invention relates to the use of optical fibers for transmission of electronic signals which are bipolar. The problem leading to the present invention arose from the desire to provide a fiber optic bus extender suitable for use with the military standard data bus MIL-STD-1553.

Fiber optic lines are ideal carriers of optical signals derived from electronic signals on a data bus. Such electronic signals may, for example, be those in aircraft internal time division command/response multiplex data buses utilized in systems integration of aircraft subsystems.

A fiber optic bus extender permits bus information to be optically transmitted to, and received from, a remote location, e.g., a location 500 meters or 1,000 meters from the bus. The fiber optic extender is able to protect the transmitted signals from noise, in addition to its other advantages over electrical cable connections. The fiber optic extender preferably has two lines, one carrying signals from a bus-connected transmitter, and the other carrying signals to a bus-connected receiver. At the other end of the extender, there may be a monitor, a remote terminal, a bus controller, or another bus. Figures 1-4 illustrate possible configurations of systems utilizing a fiber optic bus extender. In addition to the military standard data bus mentioned above (MIL-STD-1553) , there is a military standard (MIL-STD-1773) for the electrical optical interface of extenders used with 1553 buses. A handbook for 1773 users describes the "electrical/optical interface (EOI) as a circuit which accepts 1553 bus signals, performs the required conversions and transmits the message to a fiber optic cable, and also receives MIL-STD-1773 messages, performs the required conversions, and couples the message in electrical form to the MIL-STD-1553 bus cable. A pulse of light is transmitted by the 1773 transmitter when the received 1553 signal is positive

and no light is transmitted when the 1553 signal is zero or negative."

Figure 5 of this application is copied from the 1773 handbook, and is a time diagram illustrating the electrical 1553 signals and corresponding optical 1773 signals. It also illustrates the problem which is solved by the present invention.

As stated in the handbook: "Since the circuit must look ahead in time to determine whether a data word follows the end of the previous word, the transmitted 1553 message must be delayed by at least 1.5 microseconds." This delay requirement in previous fiber optic extenders has led to serious difficulties, particularly in the monitor mode, in which the remote terminal is listening but not responding. The bus extender unit previously used would stay in communication with the bus, and cause overlapping signals on the bus from different sources. The earlier bus extender had been developed for use with buses different from the 1553.

Over approximately 18 months, various possible solutions were considered and tried for the purpose of avoiding the bus extender difficulties described above, which had the effect of causing loss of bus synchronization. These efforts led to the signal controller system described and claimed in this application. Summary of the Invention

Broadly, the present invention deals with the problem of combining a three signal level bus terminal with an optical system which carries only two signal levels. Use of an added fiber or an added signal frequency would make the system more cumbersome and significantly more expensive.

The present invention provides (a) an electronic means at the transmitter for detecting the end of a given message and sending on the fiber optic extender an end-of-message signal and (b) an electronic means at the receiver for detecting the end-of-message signal and enabling the receiver to accept another message. Thus the need for waiting time is

substantially eliminated.

When the end of message detection occurs at the transmitter, a supervisory pulse is sent out, whose width is less than any other pulse in the data on the 1553 bus. This is, in effect, a "violation" of the 1553 protocol. As such, it cannot be confused with any other signal. Brief Description of the Drawings

Figures 1-5 are prior art material considered useful in understanding the background of the invention. Figure 1 is a diagram of a complete bus and bus extender system, including two bus-to-extender terminals;

Figures 2-4 show variations of the remote equipment which might be connected to the system of Figure 1;

Figure 5 shows a time diagram of the 1773 standard, in which the delay factor is illustrated;

Figure 6 is a block diagram showing electronic circuitry which handles the end-of-message pulse;

Figure 7 is a block diagram showing the transmitter of the end-of-message pulse; Figure 8 is a block diagram showing the receiver of the end-of-message pulse;

Figure 9 provides a more detailed showing of the electronic elements which create the end-of-message pulse at the transmitter end; Figure 10 is a time diagram showing the pulsing sequences at various positions in the circuitry of Figure 9;

Figure 11 provides a more detailed showing of the electronic elements which detect the end-of-message pulse at the receiver end; and Figures 12 and 13 are time diagrams showing the pulsing sequences in the old design and new design bus extender systems, respectively. Detailed Description of Specific Embodiments

Figure 1 illustrates a system utilizing a fiber optic bus extender. A bus 20, which may conform to the 1553 standard, is shown containing three stub couplers 22. The first coupler

22 is connected to a bus controller 24, and the second coupler 22 is connected to a remote terminal 26.

The third coupler 22 is shown connected to a unit 28 which connects the bus to duplex fiber optic cables 30 and 32. Unit 28 is an electrical/optical interface (EOI) unit. It has wire connections 34 and 36 with the first coupler 22. The conversion of electrical signals to optical signals, and vice versa, in unit 28 is accomplished by electrical circuitry which includes a transformer 38. The EOI unit 28 has a transmitter terminal 40 and a receiver terminal 42.

A similar second electronic/optical interface unit 44 is at a remote location from EOI unit 28, and is connected to the other ends of fiber optic cables 30 and 32. A receiver terminal 46 on EOI unit 44 is connected by cable 30 to the transmitter terminal 40 on EOI unit 28. And a transmitter terminal 48 on EOI unit 44 is connected by cable 32 to the receiver terminal 42 on EOI unit 28. EOI unit 44, like EOI unit 28, has electrical circuitry for conversion of electrical signals to optical signals, and vice versa. EOI unit 44 includes a transformer 50. The transformers 38 and 50 in the respective EOI units 28 and 44 provide protection from short circuiting for the portions of the system to which they connect. The transformers are bi-polar devices, i.e., they output positive-going and negative-going pulses, depending on the instantaneous circuit polarization.

Any such bi-polar devices have, in effect, three output values—positive voltage, negative voltage, and zero voltage.

As stated in the handbook quoted above, a pulse of light in a fiber optic cable is transmitted when the output of unit 28 or 44 is positive, and no light is transmitted when the output is zero or negative. In other words, there are three signal levels from the transformer, but only two signal conditions can be carried by the fiber optic cable. The signal transmission system comprises the bus portion having those signal levels, an electronic logic portion in which two levels (1 and 0) are used, and an optical portion in which two

levels (on and off) are used. The electronic logic portion is the link between the bus and the fiber optic bus extender.

In Figure 1, the second EOI unit 44 is shown connected to a bus monitor 52. In Figures 2-4, a box 54 represents the entire bus extender system, comprising the first EOI unit 28, the second EOI unit 44, and the two fiber optic cables (which may extend 500 to 1,000 meters).

The end of bus extender 54 remote from bus 20 is connected, in Figure 2, to a remote terminal 56. Figure 3 illustrates another system configuration, in which bus 20 is connected to two remote terminals 58 and 60; and the remote end of bus extender 54 is connected to a bus controller 62. Figure 4 shows bus extender 54 connected between two multiply coupled buses 20 and 64. Bus 20 in this system may have two remote terminals 66 and 68; and bus 64 may have a remote terminal 70 and a bus controller 72.

It is clear that the potential system arrangements are numerous. The bus extender system is the vital sub-system which permits efficient off-bus optical transmission of signals.

Figure 5 shows a timing diagram taken from the MIL-STD-1773 handbook. It illustrates the problem in trying to use a fiber optic cable between two remote bi-polar EOIs. Line 5a shows the output electrical pulses. The zero V, plus V, and minus V levels are shown at the left. At the left end 80 of the voltage line, the value is zero. A plus voltage pulse is shown at 82, and a minus voltage pulse is shown at 84. Successive voltage pulse values fluctuate between the plus and minus levels. Line 5b shows the ON and OFF conditions of the optical signal on the fiber optic cable. The optical signal is off except when the voltage on line 5a is positive.

Line 5c shows the end of a bi-polar electrical message, at which point the voltage level goes to zero, as shown by the right portion 86 of the line. This zero voltage is reached at time T ₂ . As stated in the handbook: "The EOI must accurately determine the time 'T2' in the reconstructed 1553 signal when

the 1773 message ends at 'Tl ¹ . A further requirement is that •Tl' be distinguished from *T3' . 'T3* is not the end of a message because a data sync follows the command word. Since the circuit must look ahead in time to determine whether a data word follows the end of the previous word, the transmitted 1553 message must be delayed by at least 1.5 microseconds."

Generally speaking, a timing problem exists because the encoding scheme of the bus assumes that no response is forthcoming after a predetermined time; and waiting for the time required to confirm that a message has ended can conflict with the encoding scheme.

For reasons already discussed, the required delay is not acceptable in practical bus extender systems. One solution of the problem which is believed to be in use is the addition of a third fiber optic cable to overcome the ambiguity. However, such an arrangement is cumbersome and unnecessarily expensive. Another attempted solution involves bit counting techniques, which have significant error potential. Multiple wavelengths might be used, but the complications of such an approach would be unfavorable.

The goals are to encode three EOI states into a two state carrier, while maintaining maximum "transparency", i.e., an "obliviousness" of the system to the intervention of the elements which provide the end-of-message information.

Figure 6 shows those end-of-message elements diagram¬ matically. They are included in the EOI units 28 and 44 of the systems shown in Figures 1-4. A hardwire transceiver 90 is responsible both for the conversion of electronic data to optical data prior to transmission on one fiber optic line, and also for the conversion of optical data to electronic data after reception on the other fiber optic line. A similar transceiver (not shown) is included in the remote EOI unit. As shown in Figure 6, transceiver 90 has, in addition to its other connections, two output lines 92 and 94 which input to a transmitting unit 96. Unit 96 has an output line 98

leading to fiber optic transmitter 100. Transceiver 90 has four input lines - 102, 104, 106 and 108 - which are output lines from a receiving unit 110. Unit 110 has an input line 112 from fiber optic receiver 114. The unit 96, which is replicated in the transmitter of the remote EOI, is an end-of-message pulse generator. The unit 110, which is also replicated in the receiver of the remote EOI, is an end-of-message pulse detector. The intercommunication, via the fiber optic lines, of units 96 and 110 is the means for conveying an end-of-message optical pulse, which substantially eliminates waiting time in the bus extender system, and thus eliminates the previously discussed performance problems of prior bus extender systems. The end-of-message pulse is narrower than any pulse included in the bus protocol; so no confusion is possible.

Figure 7 is a block diagram showing the basic elements of the transmitting unit 96. It comprises a data level comparator 120 and an end-of-message pulse generator 122. Inputs A and B of comparator 120 receive, respectively, the logic signal from the transceiver and the complement of that signal, i.e., logic and not-logic. In other words, at any instant during message transmission, a positive-going pulse is being received at one input, and a negative-going pulse is being received at the other input. The comparator 120 generates a pulse output on line 124 only when both inputs go to zero (the only time when the comparator inputs are equal) . The zero value is the third voltage value available from the transformer (positive, negative, zero) .

When an output pulse is sent on line 124, it signifies that the present message has ended. The pulse entering pulse generator 122 causes the latter to generate a short end of message signal, e.g., a signal having a pulse width of 100 nanoseconds (ns) .

Figure 8 is a block diagram showing the basic elements of the receiving unit 110. It includes an end-of-message discriminator 130. As long as a data bus message is being

transmitted, the discriminator 130 sends it on line 132 to data driver 134. However, if an end-of-message signal from transmitter 96 is detected, a signal on line 136 to logic unit 138 causes an output signal on line 140 to disable the receiver, and causes an output signal on line 142 to prevent transmission of the end-of-message pulse.

Figure 9 provides a more detailed showing of the electronic elements which create the end-of-message pulse from transmitter unit 96 (Figures 6 and 7) . The electronic logic signal for the fiber optic transmitter 100 (Figure 6) is carried by line 150 to one input 152 of a NOR gate 154. The output of NOR gate 154 is carried by line 156 to the fiber optic transmitter circuit. The NOR gate 154 acts as a logic inverter. The other input 158 of NOR gate 154 is connected to the output 160 of a one-shot (monostable multivibrator) 162, whose function is to generate a brief (100 ns) pulse when triggered. Triggering of one-shot 162 occurs when a negative-going edge is sensed on its input line 164. An OR gate 166 will output a 1 value on line 168 as long as a given message is in progress on the bus extender. After passing through a delay device 170, the output signal of OR gate 166 reaches the input line 164 of one-shot 162. OR gate 166 has one input 172 which is connected to the output 174 of an OR gate 176. One input 178 of OR gate 176 is connected to logic line 150. The other input 180 of OR gate 176 is connected to not-logic line 182, which carries the complement of the logic value. In other words, whenever the value at input 178 is high (1) , the value at input 180 is low (0) , and vice versa. This means that a 1 value will output from OR gate 176 on line 174 as long as message pulses are occurring. To provide a slight pulse overlap, thereby preventing an accidental loss of 1 value output while a message is being transmitted, a delay device 184 is connected between not-logic line 182 and input 186 of an OR gate 188. And another delay device 190 is connected between logic line 150 and input 192

of OR gate 188. This arrangement insures that the output signal from OR gate 188 on input line 194 of OR gate 166 will be slightly offset from the signal on its input line 172. Therefore, a 1 value will be maintained throughout the message transmission. The usefulness of the overlap feature is due to the differences in rise and fall times of the message pulses, depending on the amplitude of the incoming signals.

When both logic line 150 and not-logic line 182 drop to low (0) , the end of message is indicated. At this time the output of OR gate 166 will drop to 0. This causes a negative-going pulse edge which triggers one-shot 162, causing it to generate its short end-of-message signal. Since the value at input 152 of NOR gate is 0, the positive pulse at input 158 will cause an inverted (0) signal on line 156. This signal is subsequently converted to 1 by an inverter (not shown) on its way to the fiber optic transmitter.

Figure 10 is a time diagram illustrating the pulse timing at key points in the Figure 9 circuitry. Line 10A shows pulses at the hardwire transceiver, prior to their conversion to two value (high/low) logic. Three values exist - plus voltage, zero voltage, and minus voltage. The first and last ends of the line are at zero voltage. The other portions change between positive and negative voltage.

After the EOI has converted the bus information to two value logic, the variations of voltage are between 1 and 0, as shown on subsequent lines of Figure 10. The logic and not-logic values are shown, respectively, on lines 10B and IOC. These are the values present at inputs 178 and 180, respectively, of OR gate 176 (Figure 9) . The pulse forms on lines 10B and 10C are mirror images of one another.

Line 10D shows the pulse form at the output of OR gate 176. The value remains at 1, because one of the inputs is always at 1. Line 10E shows the slightly delayed pulse form exiting delay device 184 on line 186. Line 10F shows the slightly delayed pulse form exiting delay device 190 on line 192. The pulse forms on lines 10E and 10F are mirror images of one

another, because one receives the logic input, and the other receives the not-logic input. Line 10G shows the pulse form at the output of OR gate 188. Like the output of OR gate 176, the value remains at 1, because of the logic and not-logic inputs. The pulse form on line 10G is delayed slightly from the pulse form on line 10D.

Line 10H shows the logic output from OR gate 166. The line stays high throughout the message being transmitted. It goes low when both logic and not-logic go low, indicating that the message has ended. Line 101 shows the output on line 164. Its profile essentially matches that of line 10H, except that 101 has been delayed slightly by the delay device 170.

Line 10J shows the output from one-shot 162 on line 160. The logic voltage remains at the low level until one-shot 162 is triggered by the negative-going pulse edge 196 (line 101) . Triggering of one-shot 162 causes it to output a short end-of-message pulse 198 (line 10J) .

Figure 11 shows the primary electronic components included in the end-of-message detector associated with the fiber optic receiver. Receiving unit 110 (Figures 6 and 8) receives an electronic logic signal on line 200. That signal has been converted from the optical signal received by fiber optic receiver 114 (Figure 6) . After passing through an inverter 202a, a message pulse from the fiber optic extender has a positive-going edge on line 204 and on line 206. The normal message pulses pass through a series of inverters 202b, 202c, 202d, and 202e, and a delay device 208. Then they are output on line 210 to one input 212 of an AND gate 214. The output line 216 of AND gate 214 leads to the hardwire transceiver unit.

AND gate 214 is enabled to transmit the normal message information as long as its second input 218 has a 1 value provided by an enable line 220. The value on enable line 220 drops to 0 for a predetermined period in response to an end-of-message pulse on incoming line 200.

The circuitry in Figure 11 has three primary functions. First, it delays the normal message pulses sufficiently to permit detection of the end-of-message pulse. The end-of-message pulse is preferably 100 nanoseconds (ns) wide. The minimum pulse width during a normal message transmission is 500 nanoseconds (ns) . Delay device 208, and inverters 202b, 202c, 202d, and 202e, provide sufficient delay to permit detection of a 100 ns pulse before the normal message pulse is transmitted through AND gate 214. The second and third functions of the Figure 11 circuitry are detection of an end-of-message pulse, and removal of that pulse from the pulse train on line 216. Detection of the end-of-message pulse is primarily the function of a one-shot 222, which creates a "window" 300-400 nanoseconds wide. If no incoming pulse is completed within that period, the normal message passes through from line 200 to line 216, because the value on enable line 220 remains at 1. If, however, a shorter incoming pulse (end-of-message) is detected at one-shot 222, the result is a change at a flip-flop 224, which in turn causes a change at a flip-flop 226. The change at flip-flop 226 causes a change at a flip-flop 228, which changes the value on enable line 220 to 0, thereby blocking the message pulses on line 210 at AND gate 214. The subsequent return to 1 of the value on enable line 220 is accomplished by a signal carried on line 230 from line 210 to clock input 232 of flip-flop 228.

A more detailed explanation of the Figure 11 circuitry can begin with the logic values when the system is at rest. In an off state, with no incoming signals, the value on line 206 is 0. So 0 is the value at clock input 234 of flip-flop 226; and the Q output 236 of flip-flop 226 is at 0. The 0 on line 238 is present at the clear input 240 of flip-flop 228, and holds the Q output at 242 at 0. This causes enable line 220 to be at 0. At one-shot 222, the value at input 244 is 0 and the Q output 246 is 0. This output is connected by line 248 to the clear input 250 of flip-flop 224, holding that flip-flop in

clear condition. Therefore, its Q output 252 is 0, and its Q output 254 is 1. Line 256 connects output 254 to clear input 258 of flip-flop 226. Since the value at clear input 258 is 1, the clear constraint is removed. Therefore, a subsequent pulse leading edge can fire flip-flop 226.

When a positive-going edge from a message pulse appears on line 206, the signal at clock input 234 causes flip-flop 226 to fire. Because the clear control has been removed, this signal at 234 causes the Q value at 236 to go to 1. This 1 value is connected by line 238 to the clear input 240 of flip-flop 228, removing the clear constraint from flip-flop 228.

When a positive-going edge appears on line 230, it reaches input 232 of flip-flop 228, causing it to fire. This causes the Q value at 242 to go to 1. Enable line 220, therefore, has a 1 value, and thus permits message pulses on line 210 to pass through AND gate 214 to output line 216.

Between line 206 and line 230, the signal has been delayed by somewhat more than 100 nanoseconds (e.g., 350 ns). Delay device 208 is a 350 ns delay, and the series of inverters 202 causes a slight additional delay (e.g., 20 ns) . This permits a 100 ns end-of-message pulse to be detected.

The positive edge on line 206 causes the one-shot 222 to fire, i.e., a 1 value from Q output 246 is sent on line 248 to the clear input 250 of flip-flop 224. The period during which this 1 output at Q is maintained is the 300-400 nanoseconds for which the one-shot 222 is designed. During this period, the clear constraint on flip-flop 224 is removed. It will fire if a positive edge is received at its clock input 260. Such an edge will occur if an end-of-message pulse enters on line 200. If a 100 nanosecond pulse arrives, its negative-going edge will be changed to a positive-going edge by inverter 202b. This inverted positive edge will be carried by line 262 to input 260 of flip-flop 224, causing the flip-flop to fire. This changes the 1 value at Q output 254 to 0, and takes clear input 258 of flip-flop 226 to 0. This

in turn takes Q output 236 of flip-flop 226 to 0, and also takes clear input 240 of flip-flop 228 to 0. As a result, Q output 242 of flip-flop 228, which controls the enable line 220, goes to 0. The AND gate 214 is disabled; and it does not pass through any pulses, including the end-of-message pulse. When the firing period of one-shot 222 ends (after 300-400 ns), its Q value at 246 returns to 0, and this value at clear input 250 of flip-flop 224 clears that flip-flop. Its §Q output value at 254, therefore, becomes 1. This value, conveyed by line 256 to the clear input 258 of flip-flop 226 removes the clear constraint. Therefore, a subsequent positive-going pulse on line 206 can fire flip-flop 226. So the system is ready to start a new message. A new message will often be a response to, or acknowledgement of, the just concluded message.

A one-shot 264 is provided, which has its input 226 connected to enable line 220. One-shot 264 fires when the enable goes from an on condition to an off condition. It allows for propagation delays, in order to prevent problems due to differences in transition speeds from high to low or vise versa.

Figures 12 and 13 are time diagrams of the old and new designs, respectively. The old design is that used by the assignee of the present invention prior to discovering the need for a separate end-of-message signal.

In Figure 12, line 12A shows pulses on the bus, before or after their conversion to high/low logic. Three values exist - positive voltage, zero voltage, and negative voltage. A zero voltage condition exists between messages, at line 270, indicating that a message has ended. The last pulse in the message occurred at 274. The total of 4 microseconds (μs) indicates how quickly a remote terminal can respond to a bus controller command. If a 4 μs wait were incorporated, a new message would have begun with pulse 276, causing signal confusion and loss of synchronization.

Line 12B shows the optical pulses; and line 12C shows the voltage logic pulses from the optical receiver. Lines 12D and 12E show, respectively, the logic outputs from two flip-flops in the system. And line 12F shows that the combination of high values on lines 12D and 12E causes a continuous high value, which blocks out the dead (zero voltage) portion 270 in line 12A. The result is a failure to distinguish the end of one message and the start of a new message. Stated in another way, a timer was started and restarted on every edge of the incoming data. The duration of the timer was too long for those cases where a remote terminal would respond faster than the width of the timer. The EOI would not give up the bus connection soon enough. Line 12G shows the receiving unit bus output, having high, low, and zero values. The zero value (end-of-message) time, shown by dashed line 278, has not been recognized by the communication system.

Figure 13 is a time diagram showing how the brief end-of-message pulse (Figures 6-11) solves the problem illustrated in Figure 12. Line 13A represents the on/off optical transmitter output. The end of the present message occurs at 280; and the 100 ns pulse is generated at 282. Line 13B shows the logic pattern at the input of the optical receiver. It has the same pulse pattern as line 13A. Line 13C shows the enable pattern provided by the end-of-message detection electronics. The pulse flow is disabled during the low period 284. Line 13D shows the stripped signal at the receiver, after the end-of-message pulse 282 has been removed. Line 13E shows the three level signal values at the receiving transceiver. The receiver is off the bus at dashed line 286, and has a zero voltage value for a period 288 before a new data message starts at 290. In the system represented in Figure 13, the time required to determine that a data message has ended is too short to cause loss of synchronization. From the foregoing description, it will be apparent that the apparatus and method disclosed in this application will

provide the significant functional benefits summarized in the introductory portion of the specification.

The following claims are intended not only to cover the specific embodiments and method disclosed, but also to cover the inventive concepts explained herein with the maximum breadth and comprehensiveness permitted by the prior art.

What is claimed is: