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Patent Searching and Data


Title:
FIELD-EFFECT SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2000/022679
Kind Code:
A1
Abstract:
A buried gate region, a buried gate contact region, and a gate contact region are provided in an SiC substrate. Therefore, a depletion layer extends into a channel region, so that the breakdown strength is strong in a normally-off state. When a voltage lower than the built-in voltage is applied to the gate, the depletion layer is narrowed, and the on-resistance is lowered. When a voltage higher than the built-in voltage is applied to the gate, holes are injected from the gate, and conductivity modulation is caused, thereby lowering the on-resistance.

Inventors:
SUGAWARA YOSHITAKA (JP)
ASANO KATSUNORI (JP)
Application Number:
PCT/JP1999/005551
Publication Date:
April 20, 2000
Filing Date:
October 07, 1999
Export Citation:
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Assignee:
KANSAI ELECTRIC POWER CO (JP)
SUGAWARA YOSHITAKA (JP)
ASANO KATSUNORI (JP)
International Classes:
H01L21/04; H01L21/329; H01L21/331; H01L21/332; H01L29/10; H01L29/24; H01L29/739; H01L29/744; H01L29/749; H01L29/772; H01L29/78; (IPC1-7): H01L29/80; H01L29/74; H01L29/78
Foreign References:
EP0656646A11995-06-07
JPS5295984A1977-08-12
JPS57172765A1982-10-23
Other References:
AGARWAL A.K. ET AL., INTERNATIONAL ELECTRON DEVICES MEETING, 1996, pages 225 - 230, XP002935547
CHARLES E. WEITZEL ET AL., IEEE TRANSACTION ON ELECTRON DEVICES, vol. 43, no. 10, October 1996 (1996-10-01), pages 1732, 36 - 37, XP002935548
Attorney, Agent or Firm:
Higashima, Takaharu (Umeda 3-chome Kita-ku, Osaka-shi Osaka, JP)
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