Title:
FIELD-EFFECT TRANSISTOR, MEMORY AND PREPARATION METHOD THEREFOR, SEMICONDUCTOR ARRAY, AND TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2023/184927
Kind Code:
A1
Abstract:
Provided in the embodiments of the present application are a field-effect transistor, a memory and a preparation method therefor, a semiconductor array, and a transistor. The field-effect transistor comprises a stacked structure and two semiconductor structures, wherein the stacked structure comprises a drain structure, a gate structure and a source structure, which are sequentially stacked in a first direction above a substrate, and further comprises a gate insulation structure, which is wrapped around the periphery of the gate structure. A drain structure, a gate structure and a source structure are stacked in a direction perpendicular to a substrate to form a stacked structure, and orthographic projections of the drain structure and the source structure on the substrate at least partially overlap with each other, such that the structure of a field-effect transistor can be simplified, and both the level of difficulty and the cost of preparing the field-effect transistor can be reduced.
Inventors:
DAI JIN (CN)
YIN XIAOMING (CN)
YIN XIAOMING (CN)
Application Number:
PCT/CN2022/124169
Publication Date:
October 05, 2023
Filing Date:
October 09, 2022
Export Citation:
Assignee:
BEIJING SUPERSTRING ACADEMY OF MEMORY TECH (CN)
International Classes:
H01L29/78; H01L21/336
Foreign References:
| CN105981177A | 2016-09-28 | |||
| CN105453267A | 2016-03-30 | |||
| CN101399207A | 2009-04-01 | |||
| CN114242780A | 2022-03-25 | |||
| JP2004327615A | 2004-11-18 |
Attorney, Agent or Firm:
LIFANG & PARTNERS (CN)
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