Title:
FLIP-FLOP AND INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/184395
Kind Code:
A1
Abstract:
A flip-flop (700) and an integrated circuit, wherein same are used to reduce the probability of the occurrence of the phenomenon of metastability of a flip-flop. The flip-flop (700) comprises: a first latch (701), a second latch (702), a delay unit (703), a detection unit (704), a switching unit (705) and a third latch (706), wherein the delay unit (703) is used to delay a first clock signal and then output a second clock signal; the first latch (701) is used to latch or output a data signal according to the second clock signal; the latch (702) is used to latch or output the data signal according to the first clock signal; the detection unit (704) is used to detect whether the first latch (701) or the second latch (702) is in a metastable state, and output a control signal to the switching unit (705) based on a detection result; the switching unit (705) is used to choose, according to the control signal, to output an output signal of the first latch (701) or an output signal of the second latch (702); and the third latch (706) is used to latch or output an output signal of the switching unit (705).
Inventors:
JI BINGWU (CN)
ZHAO TANFU (CN)
ZHOU YUNMING (CN)
FAN MIN (CN)
LI ZHIYAN (CN)
WANG YUNPENG (CN)
ZHAO TANFU (CN)
ZHOU YUNMING (CN)
FAN MIN (CN)
LI ZHIYAN (CN)
WANG YUNPENG (CN)
Application Number:
PCT/CN2018/116241
Publication Date:
October 03, 2019
Filing Date:
November 19, 2018
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H03K3/037
Foreign References:
| CN101431320A | 2009-05-13 | |||
| CN105406839A | 2016-03-16 | |||
| CN104796113A | 2015-07-22 | |||
| CN104767516A | 2015-07-08 | |||
| US20070236254A1 | 2007-10-11 |
Attorney, Agent or Firm:
TDIP & PARTNERS (CN)
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