A SWITCHED CAPACITOR RESISTIVE DIVIDER

[0001] This relates generally to free running oscillators used with frequency locked control loops.

BACKGROUND

[0002] Free running oscillators, in comparison to PLLs (phase locked loops), avoid the requirement for a PLL reference clock, and require significantly less area and power, even when implemented as an FLL (frequency locked loop) oscillator/clock. FLLs (incorporating free-running oscillators) are an acceptable alternative to a PLL in systems with sufficient tolerance for phase noise and frequency variation.

[0003] One application is a high frequency (300 MHz-3000 MHz) oscillator as the modulating clock in an OOK (on-off keying) based transmission and envelope detection receiving system. Because the receiver is an envelope detector, phase noise of the modulating clock is less important. Also, a certain variation in frequency is acceptable, because primarily the receiver/detector responds to amplitude and not frequency.

[0004] Another application is a clocked power converter, where phase noise is not critical, and some error in frequency is acceptable.

[0005] Use of high frequency clocking in signal chain applications ordinarily requires accounting for EMI (electromagnetic interference) design considerations. Spread spectrum techniques can be used for spreading the EMI energy over a certain frequency band, accounting for frequency deviation as a percentage of center frequency, and spread spectrum modulation frequency.

SUMMARY

[0006] For generating a clock with a free running oscillator based on a frequency locked loop (FLL) to avoid using a phase locked loop, an FLL oscillator/clock with an FLL control loop includes a switched capacitor resistive divider.

[0007] In described examples, generating a clock using an FLL (frequency locked loop) oscillator circuit includes: (a) generating an oscillator signal FLL clk with a frequency fosc based on an oscillator control signal; (b) generating the oscillator control signal based on a frequency control signal representative of the frequency of the FLL clk output of the FLL oscillator; and (c) generating the frequency control signal based on the frequency of the FLL clk, using a switched-capacitor resistor-divider that includes a resistor and a switched capacitor coupled at an R-divider node by (i) switching the switching capacitor in response the FLL clk to convert the frequency fosc to a switched-cap resistance and (ii) outputting the frequency control signal from the R-divider node based on voltage division provided by the resistor and the switched-cap resistance.

[0008] In described examples, the methodology includes: (a) generating a spread spectrum control signal corresponding to a spread spectrum modulation function; (b) modulating the frequency control signal with the spread spectrum control signal; (c) generating an FLL control signal based the frequency control signal with spread spectrum modulation; and (d) generating the oscillator control signal with spread spectrum modulation based on the FLL control signal. As a result, the FLL oscillator generates FLL clk with spread spectrum modulation. In described examples, the spread spectrum control signal is generated with an RC relaxation oscillator including a comparator with inverting and noninverting inputs and an output, including: (a) providing a negative feedback RC transition voltage to the inverting input of the comparator, based on an RC circuit characterized by an RC time constant; (b) generating a tripping threshold voltage by switching between a V _TH upper tripping threshold voltage, and a V _TL lower tripping threshold voltage, with switching controlled by the comparator output; (c) providing the tripping threshold voltage as a positive feedback tripping threshold voltage to the noninverting input of the comparator, such that the negative feedback RC transition voltage is truncated (corresponding to the V _TH and V _TL tripping threshold voltages), and substantially triangular; and (d) generating the spread spectrum control signal based on the substantially triangular truncated RC transition voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 illustrates an example embodiment of an FLL oscillator/clock generator, including a free-running FLL oscillator, operating with an FLL control loop that includes a switched-cap resistor divider and a feedback error amplifier, and including an SSC (spread spectrum clocking) generator interfaced to the FLL loop.

[0010] FIGS. 2A and 2B illustrate an example embodiment of an SSC (spread spectrum clocking) generator that can be used with the example FLL clock generator in FIG. 1.

[0011] FIGS. 2C and 2D illustrate triangular SSC modulation based on RC truncation.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0012] Example embodiments and applications illustrate various features and advantages of an FLL (frequency locked loop) oscillator/clock generator, including a control loop with a switched capacitor resistive divider.

[0013] In brief overview, example embodiments of the FLL (frequency locked loop) oscillator/clock generator include a free-running oscillator (such as a ring oscillator), which generates an FLL clk with an FLL-controlled frequency fosc- The FLL control loop includes a switched capacitor resistor divider that converts fosc to a resistance, generating an FLL feedback voltage Vfosc used for generating a loop control signal OSC cntrl input to the oscillator. In response, the oscillator frequency locks FLL clk to fosc. In an example implementation, the FLL oscillator/clock operates with spread spectrum clocking (SSC) that provides triangular SSC modulation based on a truncated RC time constant.

[0014] In an example application, the FLL oscillator/clock can be used in a digital isolator, providing a modulating clock for OOK-based transmission with envelope-detection reception. An example clock frequency is 500MHz (e.g., supporting 100Mbps operation). SSC is useful to reduce EMI, including EMI from the transmission of unbalanced common mode currents across the isolation barrier.

[0015] In example embodiments, an FLL (frequency locked loop) oscillator circuit is suitable for use as a clock generator. The FLL clock/oscillator includes: (a) a frequency locked loop (FLL) oscillator generating an oscillator signal FLL clk with a frequency fosc based on an oscillator control signal; and (b) an FLL control loop configured to generate the oscillator control signal based on the frequency of the FLL clk output of the FLL oscillator. The FLL control loop includes: (a) a switched-capacitor resistor-divider circuit configured to provide the frequency control signal to the FLL control circuit, based on the frequency of the FLL clk; and (b) an FLL control circuit configured to provide the oscillator control signal to the FLL oscillator, based on the frequency control signal. The switched capacitor resistor-divider includes: (a) a resistor coupled at an R-divider node to a switched capacitor; and (b) the switched capacitor is configured to convert the frequency fosc of FLL clk to a resistance, such that the resistor and the switched capacitor operate as resistor divider that outputs the frequency control signal at the R-divider node.

[0016] In example embodiments, the FLL oscillator further includes a spread spectrum clocking (SSC) generator configured to generate a spread spectrum control signal corresponding to a spread spectrum modulation function. For this embodiment, the FLL control circuit includes: (a) an amplifier circuit receiving the spread spectrum control signal from the SSC generator at a noninverting input, and the frequency control signal from the switched-capacitor resistor-divider at an inverting input, and outputting an FLL control signal corresponding to the frequency control signal with spread spectrum modulation; and (b) the FLL control circuit providing the oscillator control signal with spread spectrum modulation based on the FLL control signal, such that the FLL oscillator generates FLL clk with spread spectrum modulation.

[0017] In example embodiments, the SSC generator includes: (a) an RC relaxation oscillator circuit, including a comparator with inverting and noninverting inputs and an output; and (b) a tripping threshold setting circuit. The RC relaxation oscillator includes: (a) an RC circuit characterized by an RC time constant providing a negative feedback RC transition voltage to the inverting input; and (b) the tripping threshold circuit providing a positive feedback tripping threshold voltage to the noninverting input, and configured to switch between a V _TH upper tripping threshold voltage, and a V _TL lower tripping threshold voltage, with switching controlled by the comparator output, such that the negative feedback RC transition voltage is truncated (corresponding to the V _TH and V _TL tripping threshold voltages), and substantially triangular. As a result, the SSC generator outputs as the spread spectrum control signal the substantially triangular truncated RC transition voltage.

[0018] FIG. 1 illustrates an example embodiment of the FLL clock generator 100. FLL clock generator 100 includes a free-running FLL oscillator 1 10, operating with an FLL control loop that includes a switched-capacitor resistive-divider 130 and a feedback error amplifier 140. For the example implementation, SSC control is provided by an SSC generator 150.

[0019] FLL clock generator 100 outputs (from FLL oscillator 1 10) an FLL clk with a frequency fosc controlled by the FLL control loop. Switched-cap R-divider 130 converts fosc to an FLL control voltage Vfosc that is input to error amplifier 140, which also receives an SSC control voltage V _REF ss from SSC generator 150.

[0020] An LDO (low dropout) regulator provides a clean supply VLDO for each of the FLL clock generator blocks, which are: FLL oscillator 1 10, switched-cap R-divider 130 and error amplifier 140, and SSC generator 150.

[0021] FLL oscillator 110 is implemented with a current-controlled ring oscillator 1 11, generating the FLL clk with frequency f _osc . The FLL clk output of ring oscillator 111 is level shifted 113 to provide the FLL clk with rail to rail swings (such as for CMOS levels). FLL clk (after level shifting) is passed through a break-before-make timing generator 121 for input to switched-cap R-divider 130.

[0022] Switched-cap R-divider 130 includes a resistor Rref and a switched capacitor Csw that form a resistor divider Rref/Csw, with the resistor divider output available at node Nl . FLL clk with frequency fosc controls the switched-capacitor Csw, effectively converting frequency fosc to a resistance. Switched-cap R-divider 140 (resistor divider Rref/Csw) converts fosc to an FLL feedback voltage Vfosc at the output Nl . A capacitor Ci _pf can be included to reduce ripple.

[0023] The FLL feedback voltage Vfosc from switched-cap R-divider 130 is input to error amplifier 140.

[0024] Error amplifier 140 includes an amplifier 141 providing gate drive to a current control Mpcs (PMOS) 143, which is source connected to the VLDO supply. Amplifier 141 receives the FLL control voltage Vfosc (inverting input), and an SSC modulation voltage V _REF ss (noninverting input) from SSC Generator 150, and outputs an FLL control voltage FLL cntrl that controls current through Mpcs 143, which is output as a oscillator control current OSC cntrl.

[0025] The OSC cntrl current from error amplifier 140 is input to ring oscillator 111 in FLL oscillator 110, closing the FLL control loop.

[0026] FLL oscillator 110 converts the OSC cntrl current to an OSC cntrl voltage for ring oscillator 111. In response, ring oscillator 111 outputs the FLL clk (level shifted) at the desired fosc based on OSC cntrl generated by the FLL control loop.

[0027] The FLL control voltage Vfosc from switched-cap R-divider provides FLL/fosc feedback control for the FLL clk output of ring oscillator 111. Accordingly, the FLL control loop could be designed to provide FLL/fosc feedback control based solely on the FLL control voltage Vfosc provided by the switched-cap R-divider, and input to error amplifier 140. In this implementation, the FLL cntrl voltage used for driving current control Mpcs 143 would correspond to Vfosc, and the OSC cntrl current from Mpcs 143 would lock FLL clk to fosc.

[0028] For the example embodiment, FLL clk is SSC modulated. Amplifier 111 combines the FLL control voltage Vfosc from switched-cap R-divider 130 with the SSC modulation voltage VREF ss from SSC generator 150. Negative feedback that drives Vfosc to VREF ss (steady state), effectively SSC modulating the FLL cntrl output of amplifier 141.

[0029] As a result, the OSC cntrl current used for controlling ring oscillator 111 is SSC modulated, which SSC modulates the FLL clk output form the ring oscillator (SSC modulating fosc).

[0030] The FLL closed loop negative feedback generates an FLL clk that is frequency locked to the desired fosc, based on Vfosc from the from switched-cap R-divider 130, and SSC modulated based on VREF ss from SSC generator 150. The value of the switched-capacitor resistor is (l/fosc*Csw), so that the feedback loop establishes the following relations:

LDO (1+foscRrefCsw) ⁼ Vf _osc ~ VREF SS

fosc = (VLDO- REF_Ss) (RrefCsw fosc) ~ VREF_SS

Accordingly, without SSC modulation, the FLL control loop would control fosc based on the FLL feedback voltage Vfosc. With SSC modulation, the negative feedback at amplifier 111 operates to lock Vfosc to V _RE F _SS _> SSC modulating FLL clk (with a fundamental frequency fosc, driven by the Vfosc loop).

[0031] The FLL feedback voltage V _fosc (provided by the switched capacitor resistor divider RrefCsw) is referenced to (proportional to) VLDO- AS a result, oscillator frequency f _osc depends only on the R _ref Csw time constant. Any PVT variation in the LDO voltage VLDO is cancelled out and does not affect the oscillator frequency fosc-

[0032] Controlled poly resistors are recommended. At the same time, Csw can be an MOS oxide based capacitor, such as a poly-nwell capacitor, which has a well-controlled process variation. For example, an oscillator frequency fosc varying within +/-13% across PVT can be built using a design based on the example embodiment. Using trim for process variation in the resistors and capacitors can further improve oscillator variation to just temperature variation (such as +/-3.5%).

[0033] FIGS. 2A and 2B illustrate an example embodiment of an SSC (spread spectrum clocking) generator 250 that can be used with the example FLL clock generator (SSC generator 150) in FIG. 1. Controlled spread spectrum clocking can be achieved with a substantially fixed frequency deviation as a percentage of center frequency, and a substantially fixed SSC modulation frequency. SSC generator 250 is supplied by VLDO-

[0034] SSC generator 250 provides triangular SSC modulation based on truncated RC time constant. As illustrated in FIG. 2C, for an efficient spread spectrum (close to uniform emissions spread in the spread spectrum band), SSC is achieved with a near triangular spread spectrum frequency profile.

[0035] SSC generator 250 includes an RC relaxation oscillator 260 and switched threshold (trip point) setting circuit 270. Relaxation oscillator 260 includes a comparator 261 , with negative feedback (inverting input) through R _S SF/CSSF, and positive feedback (noninverting input) from the threshold setting circuit 270. Threshold setting circuit 270 provides a switched threshold/trip point.

[0036] Relaxation oscillator 260 generates a spread spectrum voltage Vspread corresponding to the RSSF/CSSF feedback voltage. Vspread is characterized by the RSSF/CSSF rise/fall transient, based on the RSSF/CSSF time constant.

[0037] Vspread is buffered by a unity gain amplifier 270, and applied to a resistor-divider reference circuit 290, which outputs the SSC modulation voltage VREF ss-

[0038] Referring to 2A and the associated waveforms in FIG. 2B, threshold setting circuit 280 includes a switched resistor divider/ladder RT| |R _M | |RB that switches between VTH (such as 1.3V) and VTL (such as 1.1V) centered around a Vspread center voltage (such as 1.2V). VTH and VTL can be chosen so that VTH- VTL « VLDO- This implementation ensures that, while VOUT from comparator 261 (which drives the threshold setting switches S 1 S2) switches rail-to-rail from 0 to VLDO, the common mode voltage swing for VSPREAD is near triangular (such as 200mV centered around a VSPREAD center voltage of 1.2V).

[0039] Switching the noninverting input between the switched VTH VTL thresholds/trip points effectively truncates the RSSF/CSSF rise/fall transient, so that Vspread is generated based on the initial, substantially linear, part of the RC transient. As illustrated in FIG. 2D, in the initial part of the transient (beginning of the first RC time constant), the resulting Vspread voltage is substantially linear, providing a substantially triangular SSC modulation function.

[0040] The values of RSSF and CSSF can be chosen, so that the relaxation oscillator oscillates at an example frequency of 60kHz. In this implementation, the swing at VSPREAD is 200mV pk-pk

[0041] The spread spectrum voltage VSPREAD is buffered by unity gain amplifier271 , and then input to resistor-divider reference 290 through a large resistor Rss- Rss (along with the resistor divider Ri||R ₂ ) attenuates the triangular Vspread voltage applied to reference circuit 290, and hence provides a relatively small SSC percentage (such as +/-2.5%). V _REF SS is used as the SSC voltage to the closed loop oscillator described earlier.

[0042] The common mode voltage of VS _PRE A _D (V _TH +V _TL )/2 (such as 1.2V) can be chosen to match the desired dc voltage of V _REF ss, so that no current flows through Rss under dc conditions (i.e., at the center point of the spread spectrum waveform).. This design makes the SSC generator modular, so that spread spectrum clocking can be configured independent of the main FLL clock generator and the FLL control loop.

[0043] SSC percentage can be controlled by the value of Rss- Ci, C ₂ and Css caps are used to: broad band the reference resistor divider R1 ||R2; and prevent filtering of the spread spectrum waveform input to the FLL control loop. Because V _TH and V _TL are proportional to V _LD O, the signal V _REF ss also remains proportional to V _LD O, even after the addition of the spread spectrum voltage Vspread. As a result, variations in V _LD O are substantially cancelled and do not affect the oscillator frequency fosc-

[0044] FIGS. 2 A and 2B include specific design example voltages that aid in describing the example embodiment and should not be construed in limiting the scope or content of the example embodiments.

[0045] Advantages of the example embodiment of an FLL clock generator include reduced frequency variation across PVT (process voltage temperature) without requiring external components (such as resistors/crystals). Reducing frequency variation across PVT enables a narrower receiver bandwidth, resulting in better rejection of out of band noise.

[0046] Advantages of the example embodiment of a spread spectrum clocking generator include a high degree of spread spectrum control, and simple integration into an FLL control loop (at a loop reference node). Spread spectrum is achieved as a fixed percentage of main loop frequency. Tight control of spread-spectrum enables the transmitter/receiver to be designed with optimum frequency variation.

[0047] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.