FRACTIONAL-WORD WRITABLE ARCHITECTED REGISTER FOR DIRECT ACCUMULATION OF MISALIGNED DATA

Title:

FRACTIONAL-WORD WRITABLE ARCHITECTED REGISTER FOR DIRECT ACCUMULATION OF MISALIGNED DATA

Document Type and Number:

WIPO Patent Application WO2006084289

Kind Code:

A3

Abstract:

One or more architected registers in a processor are fractional-word writable, and data from plural misaligned memory access operations are assembled directly in an architected register, without first assembling the data in a fractional-word writable, non-architected register and then transferring it to the architected register. In embodiments where a general-purpose register file utilizes register renaming or a reorder buffer, data from plural misaligned memory access operations are assembled directly in a fractional-word writable architected register, without the need to fully exception check both misaligned memory access operations before performing the first memory access operation.

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Inventors:

BRIDGES JEFFREY TODD (US)
AUGSBURG VICTOR ROBERTS (US)
DIEFFENDERFER JAMES NORRIS (US)
SARTORIUS THOMAS ANDREW (US)

Application Number:

PCT/US2006/006994

Publication Date:

December 07, 2006

Filing Date:

February 03, 2006

Export Citation:

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Assignee:

QUALCOMM INC (US)
BRIDGES JEFFREY TODD (US)
AUGSBURG VICTOR ROBERTS (US)
DIEFFENDERFER JAMES NORRIS (US)
SARTORIUS THOMAS ANDREW (US)

International Classes:

G06F9/312

Foreign References:

US5802556A	1998-09-01
US5933624A	1999-08-03
US4814976A	1989-03-21
US6581150B1	2003-06-17

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