The invention relates to a frequency detector system comprising a phase detector system and comprising a frequency detector coupled to said phase detector system.

The invention also relates to a frequency detector for use in such a frequency detector system, and to a phase detector system for use in such a frequency detector system, and to a half-rate phase detector for use in such a frequency detector system, and to a method for frequency detection via phase detection, and to an apparatus comprising such a frequency detector system.

Said frequency detector system is for example used in clock extraction and data regeneration circuits of an open loop configuration or a closed loop configuration (like for example a Phase Locked Loop) and can be found in an apparatus like for example an optical receiver for controlling the frequency of a clock which needs to be synchronized with incoming data.

A prior art frequency detector system is known from the article"A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s, by Ansgar Pottbacker, Ulrich Langmann, Member, IEEE, and Hans-Ulrich Schreiber, IEEE Journal of Solid State Circuits, Vol. 27, No. 12, December 1992, which discloses a frequency detector system comprising a phase detector system (PD, QPD) and comprising a frequency detector (FD) coupled to said phase detector system (PD, QPD). Said frequency detector system generates frequency control signals (up/down) for increasing/decreasing clock frequencies.

The known system is disadvantageous, inter alia, due to, in a lock situation, <BR> <BR> still controlling the clock frequency by means of idling signals (up-down-up-down etc. ). This is inefficient.

It is an object of the invention, inter alia, of providing a frequency detector system which is more efficient.

Further objects of the invention, inter alia, are providing a frequency detector for use in such a more efficient frequency detector system, and a phase detector system for use in such a more efficient frequency detector system, and a half-rate phase detector for use in such a more efficient frequency detector system, and a method for more efficient frequency detection via phase detection, and an apparatus comprising such a more efficient frequency detector system.

The frequency detector system according to the invention comprises a phase detector system for, in response to at least one data signal, generating at least one first signal and at least one second signal, and comprises a frequency detector coupled to said phase detector system for, in response to said first signal and said second signal, generating at least one frequency control signal, with said frequency control signal being a tri-state signal comprising a first or second value in a non-lock situation and comprising a third value in a lock situation.

By introducing a tri-state frequency signal having a first value like for example the value"one"indicating the clock frequency needing to be increased (first non- lock situation) and having a second value like for example the value"minus one"indicating the clock frequency needing to be decreased (second non-lock situation) and having a third value like for example the value"zero"indicating the frequency needing to remain unchanged (lock situation), said idling signals are avoided, and the efficiency of the frequency detector system is increased, and the performance has been improved.

In a double loop clock extraction and data regeneration circuit, the first (frequency controlling) loop for example comprising said frequency detector system will be either in a frequency lock situation or in frequency non-lock situation, and the second (phase controlling) loop for example comprising a bang-bang phase detector will be either in a phase lock situation or a phase non-lock situation. The first loop is coupled to a coarse-input of a controlled oscillator, and the second loop is coupled to a fine-input of said controlled oscillator. When using the frequency detector system according to the invention, the efficiency of the entire circuit will be increased, due to the controlled oscillator in the frequency lock situation no longer being controlled by the frequency detector system and being able to concentrate on the phase locking process.

A first embodiment of the frequency detector system according to the invention is defined by claim 2.

By introducing said sampling stage and said converting stage, the combining of the first signal and the second signal into said sampled signal on the one hand and said

converting of said sampled signal into said tri-state frequency control signal on the other hand have been separated from each other to allow each one of them to be constructed efficiently and to perform efficiently.

A second embodiment of the frequency detector system according to the invention is defined by claim 3.

By constructing said sampling stage through one latch, like for example (a part of) a D-flip-flop, a low cost, low complex, low power consuming and highly efficient sampling stage has been created.

A third embodiment of the frequency detector system according to the invention is defined by claim 4.

By constructing said converting stage through one transistor (in an unbalanced situation) or two transistors (in case of a balanced situation) and through one further transistor (in an unbalanced situation) or two further transistors (in case of a balanced situation), a low cost, low complex, low power consuming and highly efficient converting stage has been created.

A fourth embodiment of the frequency detector system according to the invention is defined by claim 5.

By providing said phase detector system with said first half-rate phase detector based upon two clock signals at 0 degrees and 90 degrees and with said second half-rate phase detector based upon two clock signals at 45 degrees and 135 degrees, an efficient phase detector system has been created. Compared to full-rate designs, half-rate phase detectors will offer about twice as much time for taking decisions.

A fifth embodiment of the frequency detector system according to the invention is defined by claim 6.

By providing each half-rate phase detector with three circuits each comprising two latches and a multiplexer, with said first half-rate phase detector receiving said first and second clock signals at 0 degrees and 90 degrees, and with said second half-rate phase detector receiving third and fourth clock signals at 45 degrees and 135 degrees, low cost, low complex, low power consuming and highly efficient phase detectors have been created.

Especially the number of transistors necessary for creating 12 latches and 6 multiplexers via semiconductor technology is at a low level.

Embodiments of the frequency detector according to the invention and of the phase detector system according to the invention and of the half-rate phase detector according to the invention and of the method according to the invention and of the apparatus

according to the invention correspond with the corresponding embodiments of the frequency detector system according to the invention.

The invention is based upon an insight, inter alia, that, in a lock situation, idling frequency control signals should be avoided, and is based upon a basic idea, inter alia, that these frequency control signals should be tri-state signals having two values for the non- lock situations and one value for the lock situation.

The invention solves the problem, inter alia, of providing a more efficient frequency detector system, and is advantageous, inter alia, in that the frequency detector system has an improved performance, whereby costs, complexity and power consumption are kept at the lowest level.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments (s) described hereinafter.

Fig. 1 illustrates in block diagram form a double loop clock extraction and data regeneration circuit comprising a frequency detector system according to the invention, Fig. 2 illustrates in block diagram form a frequency detector system according to the invention, Fig. 3 illustrates in block diagram form a frequency detector according to the invention, and Fig. 4 illustrates in block diagram form a phase detector system according to the invention comprising two half-rate phase detectors according to the invention.

The double loop clock extraction and data regeneration circuit shown in Fig. 1 comprises a frequency detector system 1 according to the invention in a first frequency controlling loop further comprising a Charge Pump (CP) 2, a filter 3, and a summing device 4 of which an output is coupled to a coarse-input of a controlled oscillator 5. A second phase controlling loop comprises a bang-bang phase detector 6, a Charge Pump (CP) 7, a filter 8 coupled to a fine input of said controlled oscillator 5, and a filter 9 coupled to said summing device 4. Controlled oscillator 5 generates clock signals destined for frequency detector system 1 and for bang-bang phase detector 6, which both further receive one or more data signals.

The frequency detector system 1 according to the invention shown in Fig. 2 comprises a frequency detector 10 comprising a sampling stage 20 and a converting stage 21 and comprises a phase detector system 11 comprising two half-rate phase detectors 30 and 31. The respective half-rate phase detectors 30 and 31 receive one or more data signals and clock signals and generate the respective one or more Q-phase signals (first signals) and one or more I-phase signals (second signals). Both the Q-phase signals and the I-phase signals are supplied to sampling stage 20, which generates one or more sampled signals which are supplied to converting stage 21, which further receives the I-phase signals (second signals) and which generates one or more tri-state frequency control signals.

The frequency detector 10 according to the invention shown in Fig. 3 comprises said sampling stage 20 comprising a latch 22 receiving at its data-inputs (with the upper being the normal data-input and with the lower being the inverted data-input) the Q- phase signals (first signals) and receiving at its respective clock-inputs (with the left clock- input being the normal clock-input and with the right clock-input being the inverted clock- input) the I-phase signals (second signals) from a respective normal output and an inverted output of half-rate detector 31. A first output (with the upper output being the normal output) of latch 22 is coupled to a control electrode of a first transistor 23, and a second output (with the lower output being the inverted output) of latch 22 is coupled to a control electrode of a second transistor 24.

A first main electrode of first transistor 23 forms a first output of frequency detector 10 and is coupled via a resistor 28 to a voltage supply, and a first main electrode of second transistor 24 forms a second output of frequency detector 10 and is coupled via a resistor 29 to said voltage supply. Second main electrodes of transistors 23 and 24 are coupled to each other and to a first main electrode of a first further transistor 25. A first main electrode of a second further transistor 26 is coupled to said voltage supply. Second main electrodes of further transistors 25 and 26 are coupled to each other and via a current source 27 to ground. Control electrodes of transistors 25 and 26 respectively receive the I-phase signals (second signals) from the inverted output and the normal output respectively of half- rate detector 31.

As a result, said frequency control signal, present between said first main electrodes of transistors 23 and 24, is a tri-state signal comprising a first or second value in a non-lock situation and comprising a third value in a lock situation. By introducing a tri-state frequency signal having a first value like for example the value"one"indicating the clock frequency needing to be increased (first non-lock situation) and having a second value like

for example the value"minus one"indicating the clock frequency needing to be decreased (second non-lock situation) and having a third value like for example the value"zero" indicating the frequency needing to remain unchanged (lock situation), prior art idling signals are avoided, and the efficiency of the frequency detector system is increased, and the performance has been improved.

In the double loop clock extraction and data regeneration circuit shown in Fig.

1, the first frequency controlling loop will be either in a frequency lock situation or in frequency non-lock situation, and the second phase controlling loop will be either in a phase lock situation or a phase non-lock situation. When using the frequency detector system according to the invention, the efficiency of the entire circuit will be increased, due to the controlled oscillator in the frequency lock situation no longer being controlled by the frequency detector system and being able to concentrate on the phase locking process.

Latch 22 operates in accordance with the following algorithm: In case of the I- phase signals (second signals) having a negative to positive transition, the frequency should remain unchanged (generate the value"zero"), in case of the I-phase signals (second signals) having a positive to negative transition with the Q-phase signals (first signals) being positive, the frequency is to be increased (generate the value"one"), and in case of the I-phase signals (second signals) having a positive to negative transition with the Q-phase signals (first signals) being negative, the frequency is to be decreased (generate the value"minus one").

The phase detector system 11 according to the invention shown in Fig. 4 comprises two half-rate phase detectors 30 and 31 according to the invention. Half rate phase detector 30 comprises a latch 40 receiving at its data-inputs (with the upper being the normal data-input and with the lower being the inverted data-input) the data signals and receiving at its respective clock-inputs (with the left clock-input being the normal clock-input and with the right clock-input being the inverted clock-input) the clock signals at 00 degrees. A normal output (the upper output) of latch 40 is coupled to a first normal input of a multiplexer 42, and an inverted output (the lower output) of latch 40 is coupled to a first inverted input of multiplexer 42.

Half rate phase detector 30 further comprises a latch 41 receiving at its data- inputs (with the upper being the normal data-input and with the lower being the inverted data-input) the data signals and receiving at its respective clock-inputs (with the left clock- input being the normal clock-input and with the right clock-input being the inverted clock- input) the clock signals at 00 degrees via, compared to latch 40, exchanged connections. A normal output (the upper output) of latch 41 is coupled to a second normal input of

multiplexer 42, and an inverted output (the lower output) of latch 41 is coupled to a second inverted input of multiplexer 42.

Multiplexer 42 receives at its control inputs (with the upper being the normal control-input and with the lower being the inverted control-input) said clock signals at 00 degrees via, compared to latch 40, exchanged connections.

Half-rate phase detector 30 further comprises latches 43 and 44 and a multiplexer 45, coupled to each other identically as described above, with latch 43 receiving the clock signals at 90 degrees and with latch 44 and multiplexer 45 receiving the clock signals at 90 degrees via exchanged connections.

Half rate phase detector 30 further comprises a latch 46 receiving at its data- inputs (with the upper being the normal data-input and with the lower being the inverted data-input) the output signals from the outputs of multiplexer 45 (with the upper output being the normal output and with the lower output being the inverted output) and receiving at its respective clock-inputs (with the left clock-input being the normal clock-input and with the right clock-input being the inverted clock-input) the output signals from the outputs of multiplexer 42 (with the upper output being the normal output and with the lower output being the inverted output). A normal output (the upper output) of latch 46 is coupled to a first normal input of a multiplexer 48, and an inverted output (the lower output) of latch 46 is coupled to a first inverted input of multiplexer 48.

Half rate phase detector 30 further comprises a latch 47 receiving at its data- inputs (with the upper being the normal data-input and with the lower being the inverted data-input) the output signals from the outputs of multiplexer 45 via, compared to latch 46, exchanged connections, and receiving at its respective clock-inputs (with the left clock-input being the normal clock-input and with the right clock-input being the inverted clock-input) the output signals from the outputs of multiplexer 42 via, compared to latch 46, exchanged connections. A normal output (the upper output) of latch 47 is coupled to a second normal input of multiplexer 48, and an inverted output (the lower output) of latch 47 is coupled to a second inverted input of multiplexer 48.

Multiplexer 48 receives at its control inputs (with the upper being the normal control-input and with the lower being the inverted control-input) said output signals from multiplexer 42 via, compared to latch 40, exchanged connections, and generates said Q-phase signals.

Half-rate phase detector 31 comprises latches 50,51, 53,54, 56,57 and multiplexers 52,55, 58, all coupled to each other identically as described for half-rate

detector 30, with latch 50 receiving the clock signals at 45 degrees and with latch 51 and multiplexer 52 receiving the clock signals at 45 degrees via exchanged connections, and with latch 53 receiving the clock signals at 135 degrees and with latch 54 and multiplexer 55 receiving the clock signals at 135 degrees via exchanged connections, and with multiplexer 58 generating the I-phase signals.

The frequency detector 10 shown in Fig. 3 and the phase detector system 11 shown in Fig. 4 have double connections and double transistors to fulfil the so-called balanced situation. But the invention is not limited to this balanced situation and can be used in the so-called unbalanced situation as well, with single connections and single transistors.

Said latches are for example (parts of) double edged D-flip-flops, but other kinds of latches are not to be excluded.

The expression"for"in"for K"and"for L"does not exclude that other functions"for M"etc. are performed as well, simultaneously or not. The expressions"X coupled to Y"and"a coupling between X and Y"and"coupling/couples X and Y"etc. do not exclude that an element Z is in between X and Y. The expressions"P comprises Q"and "P comprising Q"etc. do not exclude that an element R is comprised/included as well.

It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. Use of the verb"comprise"and its conjugations does not exclude the presence of elements or steps other than those stated in a claim. The article"a"or"an"preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The invention is based upon an insight, inter alia, that, in a lock situation, idling frequency control signals should be avoided, and is based upon a basic idea, inter alia, that these frequency control signals should be tri-state signals having two values for the non- lock situations and one value for the lock situation.

The invention solves the problem, inter alia, of providing a more efficient frequency detector system, and is advantageous, inter alia, in that the frequency detector system has an improved performance, whereby costs, complexity and power consumption are kept at the lowest level.