Field of the Invention

The present invention relates to a frequency discriminator. The present invention also relates to a detector which employs one or more frequency discriminators. The present invention further relates to a system which uses one or more detectors which employ one or more frequency discriminators.

Background

In many applications, such as radar warning receivers (RWRs), there is a need to detect short-pulse signals with high probability.

Frequency-swept detectors and spectrum monitors are not well-suited to being short- pulse signal detectors since they suffer low dwell times in each frequency band.

Short-pulse signals can be detected using a digital instantaneous frequency

measurement (IFM) technique based on an analogue frequency discriminator and reference is made to P. L. Herselman and J. E. Cilliers: "A Digital Instantaneous Frequency Measurement Technique using High-Speed Analogue-to-Digital

Converters and Field Programmable Gate Arrays" (2007). A conventional frequency discriminator typically comprises a splitter, a delay line, a mixer and a low-pass filter. Using the splitter, delay line and mixer, an input signal is mixed with a delayed copy. The product is fed through a low-pass filter. The frequency of a single input tone can be found using a look-up table. However, one drawback of such a system is that it can "blinded" by an extra input tone. Another drawback is that such a system tends to suffer from having a limited dynamic range.

Case: 69488PCT1 Summary

The present invention seeks to provide an improved frequency discriminator for use in IFM.

According to a first aspect of the present invention there is provided a frequency discriminator. The frequency discriminator comprises a power splitter for splitting a signal into first and second paths. The first path is configured to provide a first, straight-through signal and the second path includes a frequency-dependent element, such as a low-pass filter, so as to provide a second signal. The frequency discriminator further comprises a circuit configured to compare the first and second signals and generate an instantaneous frequency signal in dependence thereon.

Using a frequency-dependent element, such as a low-pass filter, and a comparison circuit can help to realise a simple and/ or cheap frequency discriminator.

The frequency-dependent element maybe a linear filter. The frequency-dependent element may be a low-pass filter. The low-pass filter may have a corner frequency of at least 500 MHz. The frequency-dependent element may be a high-pass filter. The frequency-dependent element maybe a Bessel filter. This can help realise a frequency discriminator having a frequency-to-voltage characteristic that is substantially linear over several octaves of frequency

The second path may comprise two or more frequency-dependent elements in series, e.g. two or more low-pass filters (having the same or similar responses) in series. This can be used to provide a stronger frequency-dependency, e.g. a filter with a steeper slope.

The circuit may comprise a first amplifier configured to amplify the first signal and a second amplifier configured to amplify the second signal. The first and second amplifiers may have a rise/fall time which is no more than 10 ns. Using amplifiers which have fast rise and fall times can help to provide a frequency discriminator capable of detecting pulses with narrow pulse width and short response time. A comparator can be used to subtract the output of one amplifier from the other. The comparator may be an analogue comparator or a digital comparator. The digital comparator may be part of a processor. The first and second amplifiers may be first and second logarithmic amplifiers respectively. Subtracting one logarithmic value from another is equivalent to taking a ratio of linear values. Using logarithmic amplifiers can help to provide a frequency discriminator which has a wide dynamic range. The circuit may include an integrated circuit comprising the first and second amplifiers. This can help achieve good temperature stability.

The circuit may comprise a differential amplifier which is configured to compare the first and second signals or third and fourth signals obtained from the first and second signals respectively, for example amplified first and second signals.

The circuit may be configured to output an instantaneous amplitude signal. The frequency discriminator may further comprise an analogue-to-digital converter arranged to sample the instantaneous amplitude signal.

The frequency discriminator may further comprise an analogue-to-digital converter arranged to sample the instantaneous frequency signal

The frequency discriminator may be a wideband frequency discriminator.

The frequency discriminator may further comprise a limiting amplifier configured to receive an input signal and output the signal to the power splitter. This can allow a low- pass filter having a steeper roll-off to be used. The frequency discriminator may be sensitive to signals in a bandwidth between a lower frequency limit and an upper frequency limit, wherein the upper frequency limit is at least 10 GHz or at least 40 GHz.

The power splitter may be a first power splitter, the frequency-dependent element may be a first frequency-dependent element, the circuit may be a first circuit and the instantaneous frequency signal may be a first instantaneous frequency signal. The frequency discriminator may further comprise a second power splitter for splitting a signal into third and fourth paths, wherein the third path is configured to provide a fifth, straight-through signal and the fourth path includes a second frequency- dependent element so as to provide a sixth signal, and a second circuit configured to compare the fourth and fifth signals and generate a second instantaneous frequency signal in dependence thereon and a third power splitter configured to split an input signal and feed the input signal to the first and second power splitters, and the first and second frequency-dependent elements have different frequency dependencies. The first and second frequency-dependent elements may both comprise low-pass filters or high-pass filters having different cut off frequencies.

The first frequency-dependent element may be a low-pass filter and the second frequency-dependent element may be a high pass filter.

The second frequency-dependent element may be a linear filter. The second frequency- dependent element may be a low-pass filter. The second low-pass filter may have a corner frequency of at least 500 MHz. The second frequency-dependent element may be a high-pass filter. The second frequency-dependent element may be a Bessel filter. The fourth path may comprise two or more frequency-dependent elements in series, e.g. two or more low-pass filters (having the same or similar responses) in series.

The second circuit may comprise a third amplifier configured to amplify the fifth signal and a fourth amplifier configured to amplify the sixth signal. The third and fourth amplifiers may have a rise/fall time which is no more than 10 ns. A second comparator can be used to subtract the output of one amplifier from the other. The second comparator may be an analogue comparator or a digital comparator. The third and fourth amplifiers may be third and fourth logarithmic amplifiers respectively. The second circuit may include an integrated circuit comprising the first and second amplifiers. The second circuit may comprise a differential amplifier which is configured to compare the fifth and sixth signals or seventh and eighth signals obtained from the fifth and sixth signals respectively, for example amplified fifth and sixth signals.

The second circuit may be configured to output a second instantaneous amplitude signal. The frequency discriminator may further comprise an analogue-to-digital converter arranged to sample the second instantaneous amplitude signal. The frequency discriminator may further comprise an analogue-to-digital converter arranged to sample the instantaneous frequency signal.

The frequency discriminator may comprise a third comparator for comparing the first and second instantaneous frequency signals.

According to a second aspect of the present invention there is provided a detector comprising a power splitter for splitting a signal into at least two paths, each path including a frequency discriminator and at least one processor configured to process signal(s) from the at least one frequency discriminator.

Thus, the frequency discriminator can be used in larger systems, for example, multiband systems. The at least one processor may comprise at least one central processing unit (CPU). The at least one processor may comprise at least one field-programmable gate array (FPGA), at least one application-specific integrated circuit (ASIC), at least one microcontroller and/ or at least one other integrated circuit. Each path may include a filter for selecting a respective frequency range. The detector may comprise at least one band pass filter. The detector may comprise a plurality of band pass filters. One or more, or each, of the band-pass filters may have a bandwidth less than one octave (i.e./// < 2f _L where /H is the upper cut-off frequency and/z, is the lower cut-off frequency). This can help to reject harmonics. One or more, or each, of the band-pass filters may have a bandwidth of between 2 and 4 GHz, for example, 3 GHz.

Each path may include an amplifier arranged to saturate at a given input level. Thus, a substantial proportion of dynamic range of a frequency discriminator can arise from frequency discrimination.

The detector may further comprise an input section for receiving an input signal and providing the signal to the detector power splitter. The input section may comprise a high-pass filter. The high-pass filter may have a cut-off frequency of 1 GHz. The input section may comprise a power limiter. The power limiter may comprise a two-stage low noise amplifier (LNA) arrangement. According to a third aspect of the present invention there is provided a system comprising a detector and a receiver. The detector is configured, in response to receiving a signal which includes component at a predetermined frequency, to identify the frequency and to cause the receiver to tune to a frequency band which includes the frequency.

The system may further comprise at least one further processor configured to characterise the signal and, in response to characterising the signal, to generate a pulse descriptor word. The system may further comprise at least one antenna coupled to the detector and the receiver. The system may be or be comprised in a radar warning receiver system.

According to a fourth aspect of the present invention there is provided a vehicle, such as an aircraft or ship, including the system.

According to a fifth aspect of the present invention there is provided a detection device comprising at least two detectors, each detector arranged to output a corresponding power level of an input signal and at least one processor configured to receive at least two measurements of power levels from respective detectors and to determine an angle of arrival.

The detection device may further comprise at least two antennas, each antenna coupled to a respective detector.

According to a sixth aspect of the present invention there is provided a system comprising a plurality of spaced detection devices and a controller, such as a computer, for receiving measurements of angle of arrival from one or more detection devices and which is configured to determine position of a signal source from measurements of angle of arrival.

According to a seventh aspect of the present invention there is provided a detection device comprising a detector and a processor configured to measure a time of arrival of a pulse received by the detector. According to an eighth aspect of the present invention there is provided a system comprising a plurality of spaced detection devices and a controller for receiving measurements of time of arrival from one or more detection devices and which is configured to determine position of a signal source from measurements of time of arrival.

According to a ninth aspect of the present invention there is provided a detection device comprising a detector, a receiver for capturing a sample of a signal and at least one processor. The detector is configured, in response to receiving a signal, to cause the receiver to capture a sample of the signal.

The at least one processor may be configured to measure a time of arrival of a pulse received by the detector. According to a tenth aspect of the present invention there is provided a system comprising a plurality of spaced detection devices and a controller for receiving measured samples from one or more detection devices and which is configured to determine position of a signal source from the samples based on time difference of arrival.

The controller may be configured to determine position of the signal source from measurements of time of arrival.

According to an eleventh aspect of the present invention there is provided a detector, comprising an input terminal (which can be coupled to an antenna and which may be coupled to the antenna directly or via a transmit/receive switch), a processor, memory storing a unique identifier, a transmitter at least one frequency discriminator according to any one of claims l to 18 configured to receive a signal from the input terminal and to output an instantaneous frequency signal to the processor, a diode configured to receive the signal from the input terminal, a comparator configured to compare an output of the diode with a threshold and, in dependence upon determining that the diode output exceeds the threshold, to output a wake-up signal to the processor and frequency discriminator. The processor is configured, in response to receiving the wake-up signal, to cause the transmitter to transmit the unique identifier and a value of frequency based on the instantaneous frequency signal. The detector may further comprise an antenna coupled to the input terminal.

The transmitter may comprise an amplifier.

The detector may further comprise a transmit/receive switch.

According to a twelfth aspect of the present invention there is provided a system comprising at least one detector, preferably at least two detectors which are spaced apart, according to eleventh aspect and a central unit in communication with the at least one detector and configured to process a signal received from a one detector.

Brief Description of the Drawings

Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which:

Figure l is a schematic block diagram of a frequency discriminator;

Figure la illustrates a path including two low-pass filters in series;

Figure 2 is a plot of amplitude against frequency of a low-pass filter;

Figure 3 is a schematic block diagram of a frequency discriminator which includes analogue-to-digital converters;

Figure 4 is a schematic block diagram of a collision detector which includes first and second frequency discriminators;

Figure 5 is a schematic block diagram of a detector;

Figure 6 is a schematic diagram of an optional input section of the detector shown in Figure 5;

Figure 7 is a schematic block diagram of a first detector which includes a plurality of paths, each path including a filter and a frequency discriminator;

Figure 8 is a schematic block diagram of a second detector which includes a plurality of paths, each path including a power-limiting amplifier, a filter and a frequency discriminator;

Figure 9 is a schematic block diagram of a third detector which includes one or more frequency discriminator processing modules;

Figure 10 is a schematic block diagram of a frequency discriminator processing module shown in Figure 9;

Figure 11 is a schematic block diagram of a pulse detection system;

Figure 12 is a schematic block diagram of an angle-of-arrival (AOA) detection device; Figure 13 is a schematic block diagram of an AOA-based positioning system comprising a plurality of AOA detection devices and a controller;

Figure 14 is a schematic block diagram of a time-of-arrival (TO A) and/or time- difference-of-arrival (TDOA) detection device;

Figure 15 is a schematic block diagram of a positioning system comprising a plurality of TOA and/or TDOA detection devices and a controller;

Figure 16 is schematic diagram of a system for detecting and locating unauthorised rf transmitters comprising a plurality of spaced low-power radio-frequency detectors; and Figure 17 is a schematic block diagram of the detector shown in Figure 16.

Detailed Description of Certain Embodiments Referring to Figure l, a frequency discriminator l is shown.

The frequency discriminator l includes a power splitter 2 which splits an RF signal 3 received from an antenna or other source and passes the RF signal (herein also referred to as the "input signal") into first and second paths 4, 5 which feed into a comparison circuit 6.

The first path 4 feeds the input signal directly into a first logarithmic amplifier 7 (such as a Hittite (RTM) HMC648LP3E Logarithmic detector). The second path 5 includes a low-pass filter 8 having a cut-off frequency, fc, which filters the input signal. The second path 5 feeds the filtered input signal into a second logarithmic amplifier 9. The low-pass filter 8 is provided by a Bessel filter (such as a TriQuint (RTM) TGB2010-SM 5 to 9 GHz Bessel filter). A single chip, dual-channel logarithmic amplifier (such as an Analog Devices (RTM) ADL5519) 10 can be used to provide the first and second logarithmic amplifiers 7, 9. Outputs of the first and second logarithmic amplifiers 7, 9 are fed into inputs of a differential amplifier 11 which provides an output signal 13 which is a measurement of instantaneous frequency. The output 12 of the first logarithmic amplifier 7 is a measurement of instantaneous amplitude. Referring also to Figure 2, the output signal 13 does not vary significantly according to the amplitude of the input signal. However, the output signal varies significantly with frequency. In particular, the amplitude of a frequency component in the output signal is proportional to the difference 14 between frequency/ (above cut-off) and the cut-off frequency, fc-

Thus, the low-pass filter 8 can be used to impart amplitude variation which depends on frequency, while the comparison circuit 6 can be used to generate a frequency- dependent output 13 that is largely independent of the amplitude of the input signal 3. Referring to Figure la, the second path 5 may include two or more low-pass filters 81, 8 ₂ in series. This maybe used to provide a steeper slope, i.e. greater frequency

dependency.

Low-pass filter(s) need not be used. Other forms for frequency-dependent elements can be used instead. For example, a high-pass filter may be used. The element preferably exhibits monotonicity. Referring to Figure 3, the instantaneous amplitude and instantaneous frequency signals 12, 13 can be sampled using a pair of analogue-to-digital converters 15, 16, preferably using the same sample clock. The resulting digital samples can be passed to a data processing system. However, the output signals do not need to be sampled. Instead, the analogue signals can be processed at system level.

There is a trade-off between how much of the dynamic range of each logarithmic amplifier 7, 9 is used to perform the frequency discrimination and how much is used to make the output insensitive to input amplitude variations. A limiting amplifier (not shown) can be used to reduce large variations in the input signal 3.

Referring to Figure 4, frequency discriminator 1 may be configured for frequency collision detection.

The frequency discriminator 1 comprises a first power splitter 2 _1; first and second paths 4i, 5i, first and second amplifiers 71, 91, a first frequency-dependent element 81 which is in the form of a low-pass filter and a first comparator li! arranged in the same way as the frequency discriminator 1 shown in Figure 1.

The frequency discriminator 1 also comprises a second power splitter 2 ₂ , third and fourth paths 4 ₂ , 52, third and fourth amplifiers 71, 91, a second frequency-dependent element 8 ₂ which is in the form of a high-pass filter and a second comparator li! arranged in the same way as the frequency discriminator 1 shown in Figure 1.

As shown in Figure 4, the frequency discriminator 1 includes a power splitter 17 which supplies the input signal 3 to the first and second power splitters 2 _1; 2 ₂ . A single power splitter can replace the first, second and third power splitters. The instantaneous frequency signals 131, 132 can be supplied to an optional comparator 18 which outputs a comparison signal 19.

When a signal 3 is received that includes two superposed (i.e. colliding) frequencies, the comparator 18 outputs a non-zero signal 19. The instantaneous frequency and amplitude signals 12 _1; 12 ₂ , 131, 132 and, if a

comparator 18 is used, the comparison signal 19 can be sampled using respective analogue-to-digital converters (not shown). At least one processor (not shown) may be used to perform the comparison of the instantaneous frequency signals in the digital domain. Thus, the comparator 18 may be omitted.

One or more frequency discriminators 1 can be incorporated into larger devices and systems, such as radar warning receivers (RWR), electronic countermeasures (ECM) and electronic intelligence (ELINT) systems, as will now be described with reference to Figures 5 to 15.

Referring to Figure 5, a detector 20 is shown. The detector 20 receives an input signal 21 which can be a combination of different signals. The detector 20 includes an optional input section 22 which can, for example filter and/or limit the input signal 21, an optional power splitter 23 for splitting the input signal 21, one or more paths 24, each path including a frequency discriminator 1, and one or more processors 25 which carry out signal processing of the outputs of each path 24 and output one or more output signals 26.

The processor(s) 25 may comprise one or more programmable central processing units (CPUs) capable of executing code read from a non-transitory medium or memory to perform the function and operations taught herein. The processor(s) 25 may be provided in microcontroller(s). The processor(s) 25 may include one or more circuits or circuitry, for example, field-programmable gate arrays (FPGAs) or application- specific integrated circuit(s) configurable or programmable to perform the functions and operations taught herein. The processor(s) 25 may include a combination of one or more programmable CPUs and one or more configurable circuits or circuitry to perform the functions and operations taught herein.

Referring to Figure 6, the input section 22 is shown in more detail. The input section 22 includes an optional high-pass filter 27, for example, having a cut-off frequency fc of 1 GHz. The input section 22 includes a diode 28 to ground which provides protection against overload and a power limiter 29 comprising, for example, first and second low- noise amplifiers (LNA) 30, 31 arranged in series. Referring to Figure 7, the detector 20 may take the form of a multi-band detector 2O1 which includes an input section 22, a power splitter 23 and multiple paths 24. As shown in Figure 7, the output of the input section 22 is fed into the power splitter 23 which splits the signal into first, second, third, fourth, fifth and sixth paths 24!, 242, 24 ₃ ,

Each path 24^ 242, 24 ₃ , 24 ₄ , 24 ₅ , 240 includes a respective filter 33!, 332, 33 _¾ 33 ₄ , 33s, 336 for selecting a respective frequency band.

. The first, second, third, fourth and fifth filters 331, 332, 33 ₃ , 33 ₄ , 33 ₅ in the first, second, third, fourth and fifth paths 24!, 242, 24 ₃ , 24 ₄ , 24 ₅ respectively are band-pass filters. The first filter 33! maybe a low pass filter. Preferably, each band-pass filter 33!, 332, 33 ₃ , 33 ₄ , 33 ₅ has a bandwidth less than one octave (i.e./// < 2f _L where /H is the upper cut-off frequency and/, is the lower cut-off frequency) to reject harmonics from limiter 28 (Figure 6). The first, second, third, fourth and fifth filters 331, 332, 33 ₃ , 33 ₄ , 33 ₅ have pass bands of 1 to 6 GHz, 6 to 9 GHz, 9 to 12 GHz, 12 to 15 GHz and 15 to 18 GHz respectively. A sixth filter 336 in the sixth path 246 is a high-pass filter having a cut off frequency of 18 GHz.

Other passbands can be used, e.g. starting at a lower or higher lowest frequency (such as 5 or 7 GHz instead of 6 GHz) and/or going up to a lower or higher highest frequency (such as 17 or 19 GHz instead of 18 GHz). Narrower or wider passbands maybe used, e.g. 2 GHz or 4 GHz instead of 3 GHz. The passband width need not be the same for all filters and/ or the passbands need not necessarily form a contiguous band.

The output of each filter 33!, 332, 33 ₃ , 33 ₄ , 33s, 33e is fed into a corresponding frequency discriminator i _t , i ₂ , i ₃ , i ₄ , i ₅ , i6.

Each frequency discriminator i _t , i ₂ , i ₃ , i ₄ , i ₅ , i6 has a low-pass filter 8 (Figure 4) that has a cut-off frequency, fc, selected according to the band. First, second, third, fourth and fifth discriminators i ₂ , i ₂ , i ₃ , i ₄ , i ₅ have respective cut-off frequencies, fc, that are the same or about the same (e.g. ± 10%) as the lower cut-off frequency,//,, of the band pass filter 33 _1; 332, 33 ₃ , 33 ₄ , 33 ₅ which feeds that discriminator. A sixth discriminator 16 has a low-pass filter 8 (Figure 3) that has a cut-off frequency,/:, which is the same or about the same as the upper cut-off frequency of the highest-frequency band pass filter, i.e. the fifth band-pass filter 33 ₅ .

Thus, each frequency discriminator i _t , i ₂ , i ₃ , i ₄ , i ₅ , is sensitive to a different band.

As shown in Figure 7, the outputs of the frequency discriminators li, i ₂ , i ₃ , i ₄ , i ₅ , are fed into the processor(s) 25, for example, to perform pulse detection.

Referring to Figure 8, the detector 20 may take the form of a multi-band detector 20 ₂ which includes an input section 22, a power splitter 23 and multiple paths 24 which includes pre-clamped frequency discriminators li, i ₂ , i ₃ , i ₄ , i ₅ , -

The multi-band detector 20 ₂ is the same as the multi-band detector 2O ₁ shown in Figure 7 except that each path 24!, 24 _¾ 24 ₃ , 24 ₄ , 24 ₅ , 240 includes a respective power- limiting amplifier 34^ 34 _¾ 34 ₃ , 34 ₄ , 34 ₅ , 340 (such as a TriQuint (RTM) TGM2543-SM 4 - 20 GHz Limiter / Low Noise Amplifier) arranged between the power splitter 23 and the filters 33i, 332, 33 ₃ , 33 ₄ , 33s, 336-

The gains of the amplifiers 341, 34¾ 343, 344, 34 ₅ , 340 are set to saturate at a given output level (for example 22 dBm) for an input level which equals or exceeds a given level (for example 10 dBm) and can be adjusted according to the expected or measured signal level. The levels need not be the same for all the amplifiers 341, 34¾ 343, 344, 345, 346. Thus, an amplified signal is provided to each frequency discriminator i _t , i ₂ , i ₃ , i ₄ , i ₅ , 16 such that most of the dynamic response arises from frequency discrimination.

Referring to Figure 9, the detector 20 may take the form of a detector 20 ₃ which includes an input section 22, an optional power splitter 23 and one or more paths 24!, 24 _¾ ...24N. Each path 24!, 24 ₂ ,...24N ₃₅ includes a respective frequency discrimination processing module 351, 35 _¾ ...,35N which outputs at least instantaneous frequency signal 131 and, optional, at least instantaneous amplitude signal 12.1. Other signals may be output.

Referring also to Figure 10, each frequency discrimination processing module 35 ₁ , 352,— ,35N may include a power splitter 36 and one or more paths 371, 37¾...,37N. Each path 37!, 37 ₂ ,...,37N may include a power-limiting amplifier 381, 382,..., 38N, a filter 39i, 392,—, 39N (which may be a low-pass filter, a band pass filter or a high-pass filter) and a discriminator 381, 382,..., 38N. Thus, the detector 20 ₃ can be arranged to be sensitive to different bands and/or power levels.

Referring to Figure 11, a pulse detection system 40 is shown.

The system 40 includes a detector 20 which may include one frequency discriminator 1 or a bank of frequency discriminators 1, a tuneable receiver 41 (such as CRFS (RTM) RFeye (RTM) Node) and at least one processor 42.

The processor(s) 42 may comprise one or more programmable central processing units (CPUs) capable of executing code read from a non-transitory medium to perform the function and operations taught herein. The processor(s) 42 may be provided by microcontroller(s). The processor(s) 42 may include one or more circuits or circuitry, for example, FPGAs or ASIC(s) configurable or programmable to perform the functions and operations taught herein. The processor(s) 42 may include a combination of one or more programmable CPUs and one or more configurable circuits or circuitry to perform the functions and operations taught herein.

As shown in Figure 11, an antenna 43 feeds an RF signal 21 to both the detector 20 and the receiver 41.

The detector 20 is wideband and has a high probability of intercept. The receiver 41 has higher sensitivity and good frequency resolution. However, it may have a slower response and lower probability of intercept. The detector 20 can be used to trigger capture of the detected signal 21 by the receiver 41. The receiver 41 can capture the signal by in-phase and quadrature (IQ) time sampling or by spectrum analysis. On detecting a signal at a particular frequency,/, the detector 20 commands the receiver 41 to tune to a band containing that frequency and to capture the remaining part of the signal pulse.

The sample can be fed into the processor(s) 42 to identify the signal and produce a pulse descriptor word (PDW). Characteristics such as pulse repetition rate and pulse width can be measured. The system 40 may also include storage 44 for storing the captured sample and/or the pulse descriptor word. Referring to Figure 12, an angle-of-arrival (AOA) detection device 50 is shown.

The AOA detection device 50 comprises an AOA measurement system 51 which includes a set of detectors 20 and a processor 52 and a set of directional antennas 53 arranged to provide up to 360-degree around a vertical axis (not shown). There may be 6 or 8 antennas. Each detector 20 is fed by a respective antenna 53.

The processor(s) 52 may comprise one or more programmable CPUs capable of executing code read from a non-transitory medium to perform the function and operations taught herein. The processor(s) 52 may be included in a microcontroller. The processor(s) 52 may include one or more circuits or circuitry, for example, FPGA(s) or ASIC(s) configurable or programmable to perform the functions and operations taught herein. The processor(s) 52 may include a combination of one or more programmable CPUs and one or more configurable circuits or circuitry to perform the functions and operations taught herein.

The detectors 20 operate simultaneously feeding amplitude values into the processor(s) 52. The processor(s) 52 compare the received power levels from each detector 20 to estimate the angle of arrival (AOA) of the signal. Referring also to Figure 13, an AOA detection 54 is shown which comprises a network of geographically-distributed AOA detection devices 50 and a controller 55 which can calculate location to provide location, P, of a transmitter 56 by triangulation. The controller 55 can take the form of a computer system, such as a laptop computer or tablet.

The AOA detection devices 50 can transmit values of locally-determined angle, Θ, to the controller 55 via a wired (e.g. Ethernet) or wireless (IEEE 802.11) network.

Referring to Figure 14, a time-of arrival (TOA)/time-difference-of-arrival (TDOA) detection device 60 is shown. The TOA/TDOA detection device 60 comprises a TOA/TDOA measurement system 61 which includes a detector 20, an optional receiver 41 (for TDOA) and a processor 62, and an antenna 63. The processor 62 receives a time reference signal 64. The processor(s) 62 may comprise one or more programmable CPUs capable of executing code read from a non-transitory medium to perform the function and operations taught herein. The processor(s) 62 may be provided by microcontroller(s). The processor(s) 62 may include one or more circuits or circuitry, for example, FPGA(s) or ASIC(s) configurable or programmable to perform the functions and operations taught herein. The processor(s) 62 may include a combination of one or more programmable CPUs and one or more configurable circuits or circuitry to perform the functions and operations taught herein.

For a time-of-arrival (TO A) measurement, when a signal is detected, the detector 20 sends a trigger to the processor(s) 62 which records the time of arrival of the signal.

For a time-difference-of-arrival (TDOA) measurement, when a signal is detected, the detector 20 commands the receiver 41 to capture a sample of the signal or the remaining part of the signal. The receiver 41 feeds the sample (for example in the form of a time series) to the processor(s) 62.

The device 60 may be configured to perform TOA, TDOA or TOA and TDOA.

The device 60 may be switchable between first, second and third modes in which it performs TOA, TDOA or TOA and TDOA respectively.

The device maybe able to perform other types of measurement, such as AO A.

Referring also to Figure 15, a TOA/TDOA detection system 65 is shown which comprises a network of geographically-distributed TOA/TDOA detection devices 60, a controller 66 which can calculate location to provide location, P, of a transmitter 67 by trilateration, and a time reference 68 which transmits a time reference signal 64. The controller 66 can take the form of a computer system, such as a laptop computer or tablet. The TOA/TDOA detection devices 60 can transmit values of locally-determined TOA and/or a locally-captured signal sample to the controller 66 via a wired (e.g. Ethernet) or wireless (IEEE 802.11) network. For TOA, the controller 66 determines a sphere of possible locations from each value of TOA (based on the location of the device) and can use a value of TOA from three or more devices to determine the location of the source.

For TDOA, the controller 66 performs correlation analysis on pairs of captured time series and determines a hyperbolic function for a pair of measurements. By using two or more pairs of measurements, intersection(s) of hyperbolas is (are) used to determine the location of the source.

The GPS or other positioning system can be used as time reference 68.

In secure, restricted or other sensitive environments in which use of communication devices is prohibited or controlled (such as in a prison or hospital), there may be a need to detect and locate unauthorised transmitters, such as mobile phones. Monitoring or geo-location systems based on POA or TDOA can be difficult to implement successfully due to the challenging propagation characteristics of a building, such as the fact that there are a large number of rooms, the presence of thick walls, and the use of metal doors, gates and wall-reinforcements. Referring to Figure 16, a frequency discriminator 1 (Figure 1) can form part of a sensor 70 which is used to listen for, detect and locate unauthorised transmitters, such as a mobile phone 71. A sensor 70 is placed in each room 72 and is assigned a unique identifier 73 (Figure 17). If a sensor 70 detects a signal 74, it transmits a report 75 to a central unit 76 including its unique identifier 73 (Figure 17), thereby identifying itself and, thus, the room 72 in which it is located. The report 75 can also include measured signal characteristics 77, such as pulse width, pulse repetition rate and frequency band.

The central unit 76 includes a processor 78 and storage 79 which contains a table 80 listing detector identifiers 73 and corresponding locations of the detector 70. It can also store reports 75. Referring to Figure 17, the detector 70 is shown in more detail. The detector 70 is powered by a battery (not shown) and so no external power supply is required.

However, the detector 70 may be connected to an external power supply, for example, so as to be trickle charged.

The detector 70 includes a wideband antenna 82 connected via a terminal 83 to a transmit/receive switch 84.

In a quiescent state, the detector 70 is set to receive and so a wideband detector 1, microprocessor 85 and transmit amplifier 86 are in a sleep state, i.e. very low power consumption state.

RF radiation (i.e. signal 74) incident on the antenna 82 is passed to a diode detector 87. The diode 87 is a passive device and so does not require input power. The output 88 of the diode 87 is compared to a reference voltage 89 by a low-power comparator 90. If the diode output 88 exceeds the reference voltage 89, the output 91 of the

comparator 90 acts as a 'wake-up' signal.

The microprocessor 85 and wideband detector 1 become active. The wideband detector 1 estimates the signal frequency, while the microprocessor 85 measures other signal characteristics, such as pulse width and time between pulses. The wideband detector 1 passes its results 92 to the microprocessor 79.

The microprocessor 85 accesses non-volatile memory 93 which stores a unique identifier 73. The unique identifier 73 is different for each sensor 70. Upon detection of a signal 74, the microprocessor 85 sets the transmit/receive switch 84 to transmit mode, and prepares and transmits a report 75 which includes the identifier 73 and frequency and pulse time information 92 via the switch 84 and antenna 82. The report 75 is transmitted, optionally via one or more nodes (not shown) to the central unit 76 (Figure 16). A processor 78 (Figure 16) determines the sensor location by identifying the received sensor identifier 73 and looking up the location in the table 80. The low power nature of the system means that the sensors 70 can be deployed with wiring into the existing power supply. Low-power data transmission methods can be used, such as BLE (Bluetooth Low Energy). The diode output 82 can additionally be routed to the analogue-to-digital input. This can be used to derive additional information concerning the received signal power level.

The transmit/receive switch 84 may be omitted and a second antenna (not shown) be provided for transmitting signals. In that case, the wideband antenna 82 feeds directly into the diode 87 and the transmit amplifier 86 feeds the second antenna.

It will be appreciated that many modifications may be made to the embodiments hereinbefore described.

The comparison circuit in a frequency discriminator may comprise different

components.