TECHNICAL FIELD

Embodiments herein relate to a frequency multiplier and a method therein. In particular, they relate to a frequency multiplier for generating an output signal with a specific frequency from an input signal in a wireless communication device.

BACKGROUND

Wireless communication devices usually comprise transceivers which comprise receivers and transmitters. A frequency multiplier, together with a low frequency oscillator, is able to provide high purity and stable signal sources for a transceiver in a wireless communication device. The frequency multiplier multiplies an input signal with a low frequency fj _n , to an output signal with a desired high frequency f _out , where f _ou t= ⁿ * fin. ^ar, d n is an integer multiplication factor. As the operation frequency of a wireless transceiver increases, e.g., at E-band or at D-band, the multiplication factor is probably large. For instance, a D-band signal source of 130 GHz to 160 GHz needs a frequency-multiplier-by- six, n=6, which is also called as a sixtupler, as the input signal frequency is from 21 .6 GHz to 26.6 GHz.

In ABBASI, M. et al., Single-Chip Frequency Multiplier Chains for Millimeter-Wave Signal Generation, IEEE TRANSACTIONS ON MICROWA VE THEORY AND

TECHNIQUES, December 2009, vol. 57, no. 12, a sixtupler is disclosed which comprises a frequency tripler, a buffer amplifier, and a cascaded frequency doubler.

There are many ways to obtain a frequency sixtupler by cascading a frequency tripler with a frequency doubler. For example, in KALLFASS, I. et al., A W-band Active Frequency-multiplier-by-six in Waveguide Package, German Microwave Conference, 2010, a frequency-multiplier-by-six is disclosed, as shown in Figure 1 . In order to avoid a bandwidth limitation of λ/4 stubs at an output of a doubler, a balanced topology is described, where a single-ended input signal is transferred into differential outputs by an active balun. The exiting frequency-multiplier-by-six has a problem of low power efficiency which is defined as:

where P _ou t denotes the output signal power at a frequency of 6*fj _n and Ρ, _η denotes the input signal power at frequency fj _n , PDC denotes Direct Current (DC) power

consumption. The power efficiency of the existing frequency sixtupler is less than or equal to 1 %. Adding a power amplifier can boost the sixtulper's output power and conversion gain, but cannot improve the power efficiency.

SUMMARY

Therefor it is an object of embodiments herein to provide a frequency multiplier with improved performance. According to a first aspect of embodiments herein, the object is achieved by a frequency multiplier for generating an output signal with a specific frequency from an input signal. The frequency multiplier comprises a first stage to receive the input signal and generate even-order harmonics of the input signal. The frequency multiplier further comprises a second stage to receive the generated even-order harmonics and generate signals with the specific frequency by multiplying, mixing and amplifying the received even-order harmonics. The second stage 202 further combines the generated signals with the specific frequency to generate the output signal with the specific frequency. Further, an impedance matching circuit is connected between the first and second stages. The frequency multiplier may further comprise a high pass or band pass filter to suppress signals with undesired frequencies.

According to a second aspect of embodiments herein, the object is also achieved by corresponding embodiments of a method in a frequency multiplier for generating an output signal with a specific frequency from an input signal. The method comprises generating even-order harmonics of an input signal in a first stage of the frequency multiplier. The method further comprises receiving the generated even-order harmonics in a second stage of the frequency multiplier via an impedance matching circuit comprised in the frequency multiplier. The method further comprises generating signals with the specific frequency in the second stage by multiplying, mixing and amplifying the received even-order harmonics. The method further comprises combining the generated signals with the specific frequency in the second stage to generate the output signal with the specific frequency. The method may further comprise selecting the output signal with the specific frequency by a high pass or band pass filter comprised in the frequency multiplier and suppressing signals with undesired frequencies.

Since the output signal with the specific frequency is generated from different mechanisms and combined at the second stage, the frequency multiplier herein achieves good conversion gain.

Thus, embodiments herein provide a frequency multiplier with improved

performance on conversion gain and power efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

Examples of embodiments herein are described in more detail with reference to attached drawings in which:

Figure 1 is a simplified circuit schematic of a frequency-multiplier-by-six according to prior art.

Figure 2 is a general view of a frequency multiplier according to embodiments herein. Figure 3 is a schematic diagram illustrating a frequency multiplier according to

embodiments herein.

Figure 4 is a flowchart depicting a method in a frequency multiplier according to

embodiments herein.

Figure 5 is a diagram illustrating an output signal at a frequency of 6 times of the input signal frequency originating from different even-order harmonics.

Figure 6 is a diagram showing conversion gain and power efficiency versus length of a transmission line according to embodiments herein.

Figure 7 is a diagram showing spectrum for an output signal of a frequency-multiplier-by-

6 according to embodiments herein.

Figure 8 is a diagram showing conversion gain and power efficiency versus input signal frequencies according to embodiments herein. Figure 9 is a diagram showing output signal powers of different order harmonics versus input signal frequencies according to embodiments herein.

Figure 10 is a diagram showing conversion gain and power efficiency versus input signal power at input signal frequency of 25GHz according to embodiments herein. Figure 1 1 is a diagram showing output signal powers of different order harmonics versus input signal power at input signal frequency of 25GHz according to

embodiments herein.

Figure 12 is a block diagram illustrating a wireless communication device in which

embodiments herein may be implemented.

DETAILED DESCRIPTION

According to some embodiments, a general view of a frequency multiplier 200 for generating an output signal with a specific frequency from an input signal is shown in Figure 2. The specific frequency is a desired frequency generated by the frequency multiplier 200. The frequency multiplier 200 comprises two cascaded stages, a first stage 201 and a second stage 202. The first stage 201 is an even-order harmonic generator, which produces a 2nd, a 4th, and a 6th, ... order harmonics of the input signal. The second stage 202 is a nonlinear converter, which receives the generated even-order harmonics and generates signals with the specific frequency by multiplying, mixing and amplifying the received even-order harmonics. The second stage 202 further combines the generated signals with the specific frequency to generate the output signal with the specific frequency. Then, the generated output signal with the specific frequency is selected by a high pass or band pass filter 204 and signals with undesired frequencies are suppressed. Further, there is an impedance matching circuit 203 connected between the first and second stages 201 ,202. The impedance matching circuit 203 is to match an output impedance of the first stage 201 to an input impedance of the second stage 202 for different frequencies.

According to some embodiments, the frequency multiplier 200 in these

embodiments referred to as a frequency multiplier 300, may be implemented by circuits shown in Figure 3, where the first stage 201 may be implemented by a circuit referred to as a first stage 301 , the second stage 202 may be implemented by a circuit referred to as a second stage 302, and the impedance matching circuit 203 may be implemented by a circuit referred to as a impedance matching circuit 303. As shown in Figure 3, the first stage 301 comprises a capacitive cross coupled transistor pair Q-|/Q-| . Although transistor Q-| is shown as a Bipolar transistor having a base, a collector and an emitter, other type of transistor, such as Field-effect transistor having a gate, a drain and a source may be used. The first stage 301 also comprises coupled degeneration inductors L at the emitters or sources of the transistor pair Q-|/Q-| . Two inductors at the emitters are coupled with a mutual inductance, M. The coupled inductors are able to transfer a sing-ended input signal into differential signal outputs to drive two transistors Q1/Q1 with 180 phase difference. Therefore, no balun is needed for the first stage 301 . As shown in Figure 3, the collectors or drains of the transistor pair Q-|/Q-| are connected together. As the first stage 201 in Figure 2, the first stage 301 in Figure 3 is an even-order harmonic generator, where the generated 2nd and other high even-order harmonics are components which will be used in the second stage 302. The second stage 302 comprises a common-emitter or common-source transistor Q ₂ .

Although transistor Q ₂ is shown as a Bipolar transistor, other type of transistor, such as Field-effect transistor may be used. Between the first stage 301 and the second stage 302, there is the impedance matching circuit 303 comprising a Direct Current (DC) decoupling capacitor C ₂ and a piece of transmission line TL. The transmission line TL acts as an impedance converter, to transfer a high input impedance to a low one.

As the frequency multiplier 200, the frequency multiplier 300 further comprises a high pass or band pass filter 304, connected between an output of the second stage 302 and an output of the frequency multiplier 300. The output signal of the frequency multiplier 300 is taken from the collector or drain of the transistor Q ₂ at the second stage

302 via the high pass or band pass filter 304. The high pass or band pass filter is used to suppress signals with undesired frequencies at the output of the frequency multiplier 300.

According to some embodiments herein , transistors Qi and Q ₂ shown in Figure 3 are configured to operate in class-B or C configuration, in a strong nonlinear manner, and therefore consumes very litter DC power.

According to some embodiments herein, the frequency multiplier 200,300 may be a frequency-multiplier-by-six and the specific frequency of the output signal is 6 times of a frequency of the input signal. The second stage 202,302 may be configured to receive the generated even-order harmonicas, such as the 2nd, 4th and 6th order harmonics. The second stage 202, 302 is configured to multiply the received 2nd order harmonic to a first signal with the frequency of 6 times the input signal frequency. The second stage 202, 302 is configured to mix the received 2nd and 4th order harmonics to a second signal with the frequency of 6 times the input signal frequency. The second stage 202, 302 is configured to amplify the received 6 ^th order harmonic to a third signal with the frequency of 6 times the input signal frequency. The second stage 202, 302 is further configured to combine the first, the second and the third signals to generate the output signal with the specific frequency. The frequency-multiplier-by-six also uses a high pass or band pass filter to suppress signals with undesired frequencies. According to some embodiments herein, the frequency multiplier 200,300 may be a frequency-multiplier-by-8. In these embodiments, the specific frequency of the output signal is 8 times of a frequency of the input signal. The second stage 202,302 is configured to receive the generated even-order harmonics, such as the 2nd, the 4th, the 6th and the 8th order harmonics. The second stage 202,302 is configured to multiply the received 2nd and/or 4th order harmonics to a first signal with the frequency of 8 times the input signal frequency. The second stage 202,302 is configured to mix the received 2nd and 6th order harmonics to a second signal with the frequency of 8 times the input signal frequency. The second stage 202,302 is configured to amplify the received 8th harmonic to a third signal with the frequency of 8 times the input signal frequency. And further the second stage 202,302 is configured to combine the first, the second and the third signals to generate the output signal with the specific frequency. The frequency-multiplier-by-eight also uses a high pass or band pass filter to suppress signals with undesired frequencies.

Corresponding embodiments of a method in the frequency multiplier 200,300 for generating an output signal with a specific frequency from an input signal will now be described with reference to Figure 4. As mentioned above, the frequency multiplier 200, 300 comprises the first stage 201 ,301 , the second stage 202,302, the impedance matching circuit 203,303 and the high pass or band pass filter 204,304. The method comprises the following actions.

Action 401

The first stage 201 ,301 of the frequency multiplier 200,300 receives an input signal and generates even-order harmonics of the input signal.

Action 402 The second stage 202,302 of the frequency multiplier 200,300 receives the generated even-order harmonics via the impedance matching circuit 203,303.

Action 403

The second stage 202,302 of the frequency multiplier 200,300 generates signals 5 with the specific frequency by multiplying, mixing and amplifying the received even-order harmonics.

Action 404

The second stage 202,302 of the frequency multiplier 200,300 combines the generated signals to generate the output signal with the specific frequency.

10 Action 405

The high pass or band pass filter 204,304 of the frequency multiplier 200,300 selects the output signal with the specific frequency and supresses signals with undesired frequencies.

15 In some embodiments wherein the frequency multiplier 200, 300 is a frequency- multiplier-by-six, then the specific frequency of the output signal is 6 times of a frequency of the input signal, the received harmonics by the second stage 202,302 comprises at least the 2nd, the 4th and the 6th order harmonics. In these embodiments, Action 403 performed by the second stage 202,302 of the frequency multiplier 200,300 comprises

20 multiplying the received 2nd harmonic to a first signal with the specific frequency; mixing the received 2nd and 4th harmonics to a second signal with the specific frequency; and amplifying the received 6th harmonic to a third signal with the specific frequency.

In some embodiments wherein the frequency multiplier 200,300 is a frequency- 25 multiplier-by-8, then the specific frequency of the output signal is 8 times of a frequency of the input signal, the received harmonics by the second stage 202,302 comprises at least the 2nd, the 4th, the 6th and the 8th order harmonics. In these embodiments, Action 403 performed by the second stage 202,302 of the frequency multiplier 200,300 comprises multiplying the received 2nd order harmonic by 4 and/or 4 ^th order harmonic by 2 to a first 30 signal with the specific frequency; mixing the received 2nd and 6th harmonics to a second signal with the specific frequency; and amplifying the received 8th harmonic to a third signal with the specific frequency.

In order to show unique features and advantages of the frequency multiplier

35 200,300 according embodiments herein, architectures and functions of the first stage 201 ,301 , the second stage 202, 302 and the impedance matching circuit 203,303 will be discussed in more detail in combination with some simulation results.

The first stage 201 ,301 is an even-order harmonics generator. In order to avoid using a balun to transfer a single-ended input into differential outputs, a differential low noise amplifier may be modified to be an even-order harmonic generator. The differential outputs of the low noise amplifier may be combined. As shown in Figure 3, the collectors or drains of the transistor pair are connected together so that the differential outputs are combined. Thus, the odd-order harmonics are suppressed due to phase cancellation, and the even-order harmonics are added in phase.

The even-order harmonic generator is put at the first stage so that the output power of the first stage 201 ,301 can be lower than that of the second stage 202,302, to get a good power efficiency. Two transistors in the transistor pair operate in class-C

configuration, in a harmonic-rich manner, which consumes very little DC power. As a result, the power consumption of the first stage 201 , 301 is low, for example, when biased at a low base voltage of 0.63V, the DC current consumption of two transistors is 3 mA only at 1 .5V DC supply voltage, and the power consumption is only 4.5 mW.

The second stage 202,302 is a nonlinear converter. The even-order harmonics generated at the first stage 201 ,301 are fed into the second stage 302 which is a common-emitter or common-source transistor. Figure 5 shows how the output signal with a specific frequency, for example 6fo, originates from different even-order harmonics generated by the first stage 201 ,301 , where fo denotes the fundamental frequency of the input signal, 2fo, 4fo, and 6fo denote the 2nd, 4th and 6th order harmonics of the input signal respectively. Due to the transistor's nonlinearity, the 2nd and the 4th order harmonics, for example, will be mixed, generating a signal at the desired or specific frequency of 6fo- In this case, the second stage 202,302 acts as a trans-conductance mixer. Furthermore, the second stage 202, 302 may also act as a single device frequency tripler, generating a signal at the desired or specific frequency of 6fo from the 2nd order harmonic. Probably the second stage 202,302 may also function as an amplifier to amplify the 6th order harmonic at the input of the second stage 202,302 and generates a signal at the desired or specific frequency of 6fo- The signals with the specific frequency of 6fo originated from different mechanisms are added inherently by the transistor at the second stage 202,302. Consequently, a high conversion gain is obtained.

However, it is difficult to investigate the operation of the second stage 302 by an analytic method. Instead, harmonic balance simulations will be carried out in order to understand the contributions of each mechanism to the frequency multiplier output. For example, the output signal with the frequency of 6fo, that is the 6th order harmonic of the input signal, obtained by means of multiplying, mixing, as well as amplifying, in a frequency-multiplier-by-6, will be calculated separately.

In example of simulations, the input signal has a power of -1 dBm and is at a frequency of 25 GHz. The base and collector bias voltages for the transistor ⁽ ¾ at the second stage 302 are 0.69 V and 1 .5 V, respectively. The DC current consumption is 7 mA. The transistor Q ₂ operates in class-B or C configuration which demonstrates strong nonlinearity.

In the simulations, the certain frequency components generated at the first stage are removed intentionally by using a series connected LC resonator with a ground terminal. The other terminal of the LC resonator is connected with the base or gate of the second transistor Q ₂ at the second stage 302. In ideal case, the magnitude of impedance of the LC resonator is 0 Ω at a resonate frequency, and larger than 600 Ω at other harmonic frequencies. The LC resonator does not affect the impedance between two stages except at the resonate frequency, since its impedance is much larger than the parallel connected base impedance of the transistor ⁽ ¾ at the second stage 302.

Firstly, two LC resonators with resonate frequency of 4fo and 6fo are used. Thus, the input of the second stage is dominated by the 2nd harmonic. The simulated output signal power at frequency of 6fo is -1 .83 dBm, that is 0.65 mW, via frequency

multiplication, for example, multiplying by 3, ^χ 3. Secondly, the 2nd and the 4th order harmonics are filtered out, the 6th order harmonic, 6fo at the input of the second stage is amplified and an output signal with power of -37.9 dBm is obtained. This output signal is so small that the amplification function of the second stage can be ignored in this special case. Thirdly, keeping all harmonics at the input of the second stage in the simulation, an output signal with power of -1 .40 dBm, that is 0.72 mW, at frequency of 6fo is obtained, which is originated mainly from nonlinear converting, i.e., multiplying and mixing. The simulation results are shown in Table 1 , where "Y" indicates that the particular harmonic presents at the input of the second stage, "N" indicates that the particular harmonic does not present at the input of the second stage. It can be found that the power of the output signal at frequency 6fo increases about 10% (from 0.65mW to 0.72 mW) when the 4th order harmonic at the input of the second stage is kept.

5

Table 1 Simulated output signal power at different cases

The impedance matching circuit 203,303 is connected between the first stage 10 201 ,301 and the second stage 202,302. The impedance matching circuit 203,303

comprises a piece of transmission line T|_ and a DC decoupling capacitor C-2. The transmission line acts as an impedance converter, to transfer a high input impedance to a low one. Using the transmission line makes it possible to up-convert impedances of the 2nd and the 4th order harmonics simultaneously. The length of the transmission line may

15 be determined by optimization of the conversion gain. Figure 6 plots the conversion gain and power efficiency of a frequency-multiplier-by-six versus the length of the transmission line, where x-axis represents length of the transmission line, y-axis to the right represents power efficiency and y-axis to the left represents conversion gain. At the optimal length of the transmission line, for example, around 1450 μιτι, the frequency-multiplier-by-six

20 achieves maximum conversion gain and power efficiency simultaneously.

The spectrum of the output signal of the frequency-multiplier-by-six according to embodiments herein is shown in Figure 7, for an input signal at frequency fo=25 GHz with a power of -1 dBm, where x-axis represents frequency and y-axis represents output signal

25 power. The output signal with the desired frequency of 6 fo=150 GHz, has a power of -1 .4 dBm, which is 15.7 dB larger than undesired harmonics ,e.g. the odd-orders and the 4th, 8th,.. order harmonics. The conversion gain is -0.4 dB and the total DC power consumption is 15 mW only. The power efficiency is 4.2% which is the highest power efficiency among the published sixtuplers.

The conversion gain versus the input signal frequency is shown in Figure 8, where x-axis represents frequency, y-axis to the right represents power efficiency and y-axis to the left represents conversion gain. The 3-dB bandwidth of the conversion gain is from 22.9GHz to 26.25GHz for the input signal, corresponding to the output signal frequency from 137.4 GHz to 157.5 GHz.

The output signal powers of the 2nd to the 6th order harmonics are shown in

Figure 9, where x-axis represents frequency and y-axis represents output signal power . The output signal power at the 1 st harmonic is below -100 dBm. It can be found that the rejection of undesired harmonics, e.g., the 2nd, 3rd, 4th, 5th is larger than 13 dB in the 3- dB bandwidth.

Figure 10 plots the conversion gain and power efficiency as a function of the input signal power at frequency fo=25GHz, where x-axis represents input signal power, y-axis to the right represents power efficiency and y-axis to the left represents conversion gain. The conversion gain peaks as the input signal power is around -1 dBm. The maximum power efficiency is 4.3% when the input signal power is 0 dBm. Figure 11 shows the output signal powers of different harmonics versus input signal power, where x-axis represents input signal power and y-axis represents output signal power . It can be seen that the output signal power will be saturated at 0.85 dBm. Further, it can be seen that the rejection of undesired harmonics is almost unchanged with input signal power.

In summary, the frequency multiplier, for example the frequency-multiplier-by-six according embodiments herein has following unique features:

There is no filter or buffer amplifier between two stages, instead an impedance matching circuit comprising a piece of transmission line and a DC decoupling capacitor is connected between the two stages.

The second stage has multi-function, for example, multiplying the 2nd order harmonic, mixing the 2nd and the 4th order harmonics, and amplifying the 6th order harmonic.

The first stage is an even-order harmonics generator without utilizing balun.

These unique features of the frequency multiplier according to embodiments herein result in following advantages: 1 . Good conversion gain and power efficiency without utilizing amplifiers.

2. All transistors in the frequency multiplier according to embodiments herein operate in class-B or C configuration with a low DC power consumption, while the output signal with a specific frequency is obtained via transistor's nonlinear converting.

3. The even-order harmonic generator without balun saves the chip area comparing with that of using a passive or an active balun, respectively.

The frequency multiplier 200,300 according to embodiments herein is suitable for millimeter or macro wave transceivers as an RF signal source generator, for example to generate E-band or D-band signals, in a wireless communication device 1200 as shown in Figure 12. The wireless communication device 1200 comprises a Transceiver 1210, wherein the frequency multiplier 200,300 may be implemented in. The wireless communication device 1200 further comprises a Memory 1220 and a Processing unit 1230.

Those skilled in the art will understand that although transistors Q-| , ⁽ ¾ in the frequency multiplier 300 as shown in Figures 3 and 4 are Bipolar Junction Transistors (BJT), the frequency multiplier 300 may comprise any other types of transistors, such as Field-Effect Transistor (FET), Metal-Oxide-Semiconductor FET (MOSFET), Junction FET (JFET), etc. When using the word "comprise" or "comprising" it shall be interpreted as non- limiting, i.e. meaning "consist at least of".

The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used.

Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appending claims.