FREQUENCY SYNTHESIZER WITH FINE RESOLUTION

BACKGROUND OF THE INVENTION

1. Field of the Invention

The field of the invention is phase-locked loop (PLL) frequency synthesisers, and applications thereof.

2. Discussion of Related Art

In a conventional phase-locked loop frequency synthesiser, the smallest frequency step is determined by the comparison (or reference) frequency at which the phase detector operates. In order to achieve a fine frequency resolution, it is therefore necessary to operate the phase detector at a low frequency. This leads to some undesirable characteristics of conventional phase-locked loop frequency synthesisers. For example, to maintain loop stability, the loop bandwidth must be set significantly lower (usually by a factor of about 10) than the comparison/reference frequency. Because the loop response time varies inversely with the loop bandwidth, this means that the loop response time is large, leading to long settling times when the frequency is changed, and to increased close-in phase noise, where close-in phase noise is the noise in the phase value as the frequency in the loop approaches the new target frequency. The reduction in loop bandwidth also increases susceptibility to microphonic effects, where microphonic effects are those in which electronic components convert mechanical perturbations into unwanted electrical signal noise. Therefore, known disadvantages of conventional phase-locked loop frequency synthesisers include long settling times when the frequency is changed, significant close-in phase noise, and increased susceptibility to microphonic effects. Some of these disadvantages have been noted in US4,234,939.

A number of methods are known which can overcome the disadvantages of conventional phase-locked loop frequency synthesisers. The principal methods known which can overcome the disadvantages of conventional phase-locked loop frequency synthesisers

include the use of fractional-N loops and of dkect digital synthesis (DDS). However, fractional-N loops are known to suffer from spurious output frequencies, and DDS devices are relatively expensive and have a relatively low operating frequency range.

Implementations of the present invention provide a phase-locked loop frequency synthesiser that overcomes at least some of the known disadvantages of the alternatives to conventional phase-locked loop frequency synthesisers; implementations avoid the output of spurious frequencies, are relatively low cost, and provide an acceptably large operating frequency range, or provide any one or more combinations of these advantages.

In an application of conventional phase-locked loop frequency synthesisers, an incoming radio frequency (RF) signal at a receiver is converted to a fixed intermediate frequency (IF). But the RF frequency resolution is limited by the properties of the one or more conventional phase-locked loop frequency synthesisers utilized. An implementation of die invention addresses this.

Further applications of conventional phase-locked loop frequency synthesisers include their use in radio transmitters /receivers, radio/TV receivers, thek use in spreading the electromagnetic noise spectrum generated by an electronic device over an increased bandwidth by varying the operating frequency of the electronic device, and their use in varying the phase and frequency of the signals derived from feedback clocks in electronic circuitry such that the signals match the reference clock of the electronic circuitry. An improved phase-locked loop frequency synthesiser may replace conventional phase-locked loop frequency synthesisers in such applications.

SUMMARY OF THE INVENTION

An implementation of the invention provides a phase-locked loop frequency synthesiser with improved characteristics relative to conventional phase-locked loop frequency synthesisers. The improved characteristics may include reduced settling times when the frequency is changed, reduced close-in phase noise, and reduced susceptibility to microphonic effects. These improved characteristics may be achieved using a comparison/reference frequency at which the phase detector in the PLL operates which is significantly higher than in conventional PLL designs. The implementation requires a main PLL, which includes the phase detector. This main PLL takes as its input the comparison/reference frequency. There is an auxiliary PLL, which uses as its comparison/reference frequency a frequency that differs from the comparison/reference frequency used in the main PLL by a small amount, δ, which is approximately equal to the smallest frequency step required to be used in the synthesiser or some submultiple thereof.

The higher comparison/reference frequencies of the two phase-locked loops (i.e. when compared with conventional PLLs) may lead to reduced settling times when the phase detector frequency is changed, for example, because the settling time is typically inversely proportional to the comparison frequency. In some embodiments of the invention, sum frequency generation between the two phase-locked loops may also be utilized in the overall frequency conversion process.

Embodiments of the invention provide systems with improved characteristics, where the improved characteristics derive from the improved characteristics of the phase-locked loop frequency synthesisers described above. Such systems may include radio receivers and radio transmitters, for example, or receivers or transmitters which function in other parts of the electromagnetic spectrum, such as for optical wavelengths, which include infra-red, visible or ultra-violet wavelengths. Such systems may also include those in which the electromagnetic waves are transmitted along conducting wires, or along optically transmissive cables such as fibre optic cables. More specifically, applications which utilize such systems may include

frequency division multiplexing on mains cables, on telephone lines, on optical fibres, or for electromagnetic waves which propagate in air or in a vacuum.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a phase-locked loop frequency synthesiser circuit diagram.

Figure 2 is a phase-locked loop frequency synthesiser circuit diagram. Figure 3 is a phase-locked loop frequency synthesiser circuit diagram.

DETAILED DESCRIPTION

In one implementation, a frequency synthesiser includes two phase-locked loops U and 12 with high, but slightly different comparison/reference frequencies which enter the circuit via transmitting media 13 and 17, as shown in Figure 1. A fine resolution in the frequency generation process is achieved through the use of a small difference between the frequencies of the two reference signals. Means are supplied for generating the comparison frequencies.

In Figure 1, the two loops are the main loop 11 and the auxiliary loop 12; the main loop 11 produces the final output frequency which propagates in the transmitting medium 16. In

Figure 1, elements 14 and 18 are phase detectors. In Figure 1, the frequency output of the auxiliary loop 12 is mixed at mixer 100 with the frequency output of the main loop 11 to produce the sum frequency and the difference frequency. The sum frequency or the difference frequency may be removed by filtering, leaving one remaining frequency. The one remaining frequency may then be used as the feedback term for the main loop. Typically, the difference frequency would be used as the feedback term for the main loop. Filtering is also employed elsewhere in the circuit of Figure 1.

In Figure 1, the reference frequencies for the main loop U and for the auxiliary loop 12 are Rl and R2, respectively. These enter the circuit via transmitting media 13 and 17, respectively, and are chosen such that

Rl = P δ

R2 = (P + 1) δ

where P is a scale factor and δ is the desired step frequency, such that: δ = R2 — Rl.

The auxiliary loop 12 has a programmable feedback divider 19 operating with a ratio N2. A programmable feedback divider is an adjustable frequency changing device. It follows that the auxiliary loop generates a frequency F _311x given by

F _aux = N2 (P + 1) δ

To enable a wide frequency coverage, it is preferable that it should be possible to vary N2 over a range of values of the order of P. Hence it would be possible to vary F _aux over a range of values of about P (P + 1) δ.

The frequency F _aux is subtracted from the output frequency F _out of the main loop U to provide the main loop's feedback term. The main loop 11, which has a programmable feedback divider 15 operating with a ratio Nl, will lock when its frequency F _main is given by the sum of its internally generated frequency Nl P δ and F _aux i.e. when

F _main = N1 P δ + N2 (P + 1) δ

= (Nl + N2) P δ + N2 δ

From Figure 1, the output frequency F _out is equal to F _main . It can be seen from the above that if N2 is increased by 1, and Nl is decreased by 1, F _out will increase by δ. It is also evident that the value of P does not affect the step size δ. However, in order to achieve continuous frequency coverage, the auxiliary loop 12 should cover a frequency range of at least about P (P + 1) δ, which may put practical limits on the value of P. In some embodiments of the invention, Rl and R2 may be derived from a common reference source, which may put further restrictions on practical values of P.

In a further embodiment of the invention, shown in Figure 2, the outputs of the main loop 21 and of the auxiliary loop 22 are mixed together at mixer 200 to generate the sum frequency and the difference frequency. In Figure 2, the reference frequencies enter the circuit via transmitting media 23 and 27, elements 24 and 28 are phase detectors, and elements 25 and 29 are integer dividers. A fine resolution in the frequency generation process is achieved through the use of a small difference between the frequencies of the two reference signals. Means are supplied for generating the comparison/reference frequencies.

In the case of the circuit shown in Figure 2, F _main is Nl P δ. If the sum frequency is used as the output frequency F _out it follows that F _out in Figure 2 in transmitting medium 26 will be given by

F _out = Nl P δ + N2 (P + 1) δ

= (Nl + N2) P δ + N2 δ

In a further embodiment of the invention, two phase-locked loops with high, but somewhat different, comparison frequencies may be used to provide high resolution tuning in a radio receiver. A fine resolution in the frequency conversion process from the input signal to the output signal is achieved through the use of a small difference between the frequencies of the first and second reference signals. Means are supplied for generating the comparison frequencies. In the embodiment of the invention shown in Figure 3, two integer-N phase locked loops 31 and 33 are used as local oscillators to perform two consecutive frequency conversions on an incoming RF signal, which enters the circuit via transmitting medium 30. PLLl 31 has a reference frequency Ql and a divider ratio Ml. PLL2 33 has frequency reference Q2 and divider ratio M2. Ql and Q2 are multiples of the desired step size δ such that

Ql = (P+l) δ Q2 = P δ

where P is a scaling factor and we have the property that δ = Ql — Q2. The first frequency conversion in the first signal mixer 36 takes the signal frequency S and converts it by sum frequency generation to IFl. IFl is therefore given by:

IFl = S + (P+l) δ Ml

The second frequency conversion in the second signal mixer 37 is a difference frequency conversion which converts IFl to the final output frequency IF2 in transmitting medium 35 given by:

IF2 = IFl - P δ M2

The two frequency conversions are equivalent to a single frequency conversion with an output frequency given by

IF2 = S + (P +1) δ Ml - P δ M2

= S + P δ (Ml - M2) + δ Ml

It will be seen from the above that if both Ml' and M2 are increased by 1, the change in output frequency IF2 will be δ. It also follows that as IFl does not appear in the final equation for IF2, the value of IFl is arbitrary to this extent, which implies that IFl can be chosen according to other factors such as ease of filtering or the re-use of existing circuitry. To allow continuous frequency coverage, IFl should vary over a range of about P (P+ 1) δ.

It will be apparent to those skilled in the art that the receiver of Figure 3 may be applied to receive electromagnetic waves within any of many regions of the electromagnetic spectrum, including regions such as those characteristic of radio waves, microwaves, infra-red radiation, visible radiation and ultra-violet radiation.

Within the circuits of Figures 1, 2 or 3, or in other circuits of the invention, filtering may be employed to allow frequencies in a particular range to propagate, thereby blocking frequencies outside the said range.

In a further embodiment of the invention, more than one auxiliary loop may be used. This has the advantage of restricting the tuning range required of the auxiliary oscillators or of the intermediate frequencies.

In a further embodiment of the invention, the value of δ could be selectable using a computer program, rather than being fixed by the circuitry. One example of an application of this embodiment of the invention is an application in a radio receiver, where a variable value of δ would enable one to scan a wide band of frequencies, or to receive broadcasts which are consistent with various different broadcasting standards.

In a further embodiment of the invention, if a sufficiently small step size δ is used, the system may be used for automatic frequency control or for sample-timing adjustment in digital receiver or transmitter systems.

In further embodiments of the invention, the circuitry of Figures 1, 2 or 3 may be used to provide a reference for another PLL. In further embodiments of the invention, one could combine two or more elements, where each element consists of the circuitry of Figures 1, 2 or 3, to enable the attainment of increased frequency resolution. This could be achieved for instance by utilising more than one auxiliary loop: this would have the benefit of limiting the frequency range over which the auxiliary loops are required to operate. In the consecutive conversion system of Figure 3, this would allow more stringent filtering of the intermediate frequencies.

A further embodiment of the invention consists of a transmitter of electromagnetic waves in which the apparatus of Figure 3 is employed to convert an input frequency into an output frequency for transmission, where the output frequency is different to the input frequency.

An example of the embodiment of the invention illustrated in Figure 3 now follows, but many further variants of the invention will be obvious to persons skilled in the art. In this example, the first PLL 31 is taken to have a comparison frequency of 100 kHz, and the second PLL 33 is taken to have a comparison frequency of 99 kHz. This implies that δ is 1 kHz and that P is 99. The incoming signal in transmitting medium 30 is taken to have a frequency S of 6.000 MHz; we wish to convert it to an IF2 value of 45.000 MHz.

By setting Ml to 1,380 the first loop oscillator (LO) 32 is set to 138 MHz, giving a IFl value of 138 + 6 = 144 MHz in transmitting medium 36. By setting M2 to 1,000 the second LO 34 is set to 99 MHz. The resulting IF2 value in transmitting medium 35 is 144-99=45.000 MHz, as desired.

Suppose now that one desires to convert an incoming signal of 5.999 MHz to 45.000 MHz using the same circuitry. Ml is increased by 1 step to 1,381, giving a first LO 32 now set to

138.1 MHz, which implies IFl = 5.999 + 138.1 = 144.099 MHz. If M2 is also increased by 1 step to 1,001 then the second LO 34 is . now set to 99.099 MHz. The resulting IF2 in transmitting medium 35 is still 45.000 MHz, as desked. It is evident that to ensure broad frequency coverage IFl should be capable of varying in. frequency over a range of about (100 x 99) kHz = 9.9 MHz in this example, which is an acceptable range. It will be apparent to those skilled in the art that variations in Ml and M2 may be used to tune to an incoming RF signal which varies by any integer multiple of 1 kHz.

Those skilled in the art will appreciate that in some cases the frequency resolution which will be achieved in implementations of the invention may be approximately equal to δ, rather than being exactly equal to δ, for various reasons such as but not limited to the signal dispersion which may occur during signal propagation, the quantitative measure of frequency resolution adopted, or non-ideal behaviour of the elements of the circuits.

In terms of response times, the two PLLs 31 and 33 will have a bandwidth of about one tenth of their frequency i.e. about 10 kHz. This suggests a response time for each PLL of the order the reciprocal of these bandwidths i.e. of the order of 100 microseconds. In contrast, a conventional PLL with a phase detector comparison frequency of 1 kHz will have a bandwidth of about one tenth of 1 kHz which is about 100 Hz. This suggests a response time of the order the reciprocal of this bandwidth i.e. of the order of 10 milliseconds. These considerations provide an indication of the order of the reduced response time that may be achieved by the phase-locked loop frequency synthesiser which is an embodiment of the invention.

Various modifications and alterations of this invention will become apparent to those skilled in the art without departing from the scope of this invention, and it should be understood that this invention is not to be unduly limited to the illustrative embodiments set forth herein.