METHODS FOR SYNTHESIZING A FREQUENCY

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Singapore Patent Application number 10201510323P filed 16 December 2015, the entire contents of which are incorporated herein by reference for all purposes.

TECHNICAL FIELD

[0002] Various embodiments relate to frequency synthesizers and methods for synthesizing a frequency.

BACKGROUND

[0003] The requirements for local oscillator and clock systems in wireless and wireline applications are increasingly stringent as the standards continuously evolve. In addition, it is desirable to have the output frequency range as wide as possible in applications such as the software-defined radio. It is challenging to achieve low-jitter, i.e. low phase noise while keeping power consumption low. Frequency synthesizers based on multiplying delay-locked loop (MDLL) and injection-locked oscillator (ILO) are promising architectures in this aspect. The MDLL is similar to the ring oscillator in which a signal traveling along the delay line is periodically replaced by a clean reference signal. As a result, the phase noise of the ring oscillator is high-filtered up to half of the reference frequency and the amount of jitter is significantly reduced. During the injection of the reference signal, the edge of the ring oscillator output is replaced or moved to the edge of the reference signal. Therefore, the edge of the reference signal should be aligned with the edge of the ring oscillator output. Any mismatch between the position of the edges of the reference signal and the edges of the ring oscillator output may increase the spur level or in some cases, cause the injection to fail. To avoid such mismatches, the frequency of the ring oscillator should be integer multiples of the reference frequency which may be difficult to implement in practical radiofrequency systems where high frequency resolution is required. Methods to resolve the abovementioned issues may include using multiphase signals of a ring oscillator or variable delay cells to synthesize fractional multiples of a reference frequency. However, using multiphase signals of the ring oscillator to synthesize fractional multiples of the reference frequency may require a large number of delay cells in the ring oscillator to achieve fine frequency resolution since the output frequency resolution is determined by the number of delay cells. Having a large number of delay cells may increase the area and power consumption. The fractional multiples of the reference signal may alternatively be synthesized using variable delay cells to delay the reference signal according to the error of a delta sigma modulator (DSM). This dynamically delayed reference signal may be aligned with the output of the oscillator even when the oscillator's output frequency is fractional multiples of the reference frequency. The dynamically delayed reference may also reduce the quantization noise of the DSM. However, this method requires the use of two independent delay cells and there may be a mismatch between the two delay cells such that the DSM noise may not be fully cancelled. In addition, the required dynamic range of the delay cell may depend on the output frequency, so it may be difficult to optimize the design over a wide output frequency range. Alternatively, Finite Impulse Response (FIR) filtering method may be used. However, filtering may not sufficiently suppress the quantization noise of the DSM. Moreover, since the FIR filter may be implemented by several on-chip capacitors, it may occupy a large area. Another method for synthesizing the fractional frequency may be to use adjustable delay cell and have the output frequency resolution determined by the least significant bit of the delay cell. However, the output frequency resolution may be very sensitive to process, voltage and temperature variation. The dynamic range requirement of the delay cell may also depend on the output frequency.

[0004] Therefore, a new method for synthesizing frequency is required to overcome the abovementioned deficiencies of existing methods.

SUMMARY

[0005] According to various embodiments, there may be provided a method for synthesizing a frequency, the method including: generating a fractional frequency signal based on a reference signal using a fractional frequency signal generator including a delay-locked loop, wherein the delay-locked loop includes a plurality of delay cells; locking an oscillator to the fractional frequency signal using a phase-locked loop circuit, wherein a frequency of an output of the phase-locked loop circuit is on average, at least substantially equal to a frequency of the fractional frequency signal; removing fractional noise from the fractional frequency signal with a compensation loop; and calibrating respective delay mismatches of the plurality of delay cells.

[0006] According to various embodiments, there may be provided a frequency synthesizer including: a fractional frequency signal generator configured to generate a fractional frequency signal based on a reference signal; wherein the fractional frequency signal generator includes a delay-locked loop including a plurality of delay cells; a phase-locked loop circuit configured to be locked to the fractional frequency signal; a digital calibration circuit configured to calibrate respective delay mismatches of the plurality of delay cells; wherein a frequency of the fractional frequency signal is on an average, at least substantially equal to a frequency of an output of the phase-locked loop circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the invention. In the following description, various embodiments are described with reference to the following drawings, in which:

[0008] FIG. 1 shows a flow diagram of a method for synthesizing a frequency according to various embodiments.

[0009] FIG. 2 shows a flow diagram of a method for synthesizing a frequency according to various embodiments.

[0010] FIG. 3 shows a frequency synthesizer according to various embodiments.

[0011] FIG. 4 shows a timing diagram illustrating the problems with using the conventional injection-locking technique in frequency synthesis.

[0012] FIG. 5 shows a block diagram of a frequency synthesizer according to various embodiments.

[0013] FIG. 6 shows a block diagram of a fractional reference frequency generator according to various embodiments.

[0014] FIG. 7 shows a timing diagram of a phase rotator according to various embodiments, when the phase rotator has a normal rotating direction.

[0015] FIG. 8 shows a timing diagram of a phase rotator according to various embodiments, when the phase rotator has a reversed rotating direction.

[0016] FIG. 9 shows a block diagram showing part of the fractional reference frequency generator, the noise cancellation circuit and part of the phase-locked loop. [0017] FIG. 10 shows a timing diagram of the output of the phase rotator and the output of the calibrated signal, TCAL with mismatch in the delay-locked loop (DLL).

[0018] FIG. 11 shows a block diagram of the digital calibration for mismatches in the DLL.

[0019] FIG. 12 shows a graph showing the simulated phase noise of a frequency synthesizer in an ideal situation without any delay mismatches in the DLL.

[0020] FIG. 13 shows a graph showing the simulated phase noise of a frequency synthesizer, with delay mismatches in the DLL.

[0021] FIG. 14 shows a graph showing the control input signals of the delay cells after the calibration is enabled.

[0022] FIG. 15 shows a graph showing the delay of the delay cells after the calibration is enabled.

[0023] FIG. 16 shows a graph showing the resulting phase noise after the calibration is performed.

[0024] FIG. 17 shows a graph showing the relationship between phase noise and frequency.

[0025] FIG. 18 shows a graph showing the relationship between phase noise and frequency.

[0026] FIG. 19 shows a table summarizing the jitter measured in the simulation.

DESCRIPTION

[0027] Embodiments described below in context of the frequency synthesizers are analogously valid for the respective methods, and vice versa. Furthermore, it will be understood that the embodiments described below may be combined, for example, a part of one embodiment may be combined with a part of another embodiment.

[0028] It will be understood that any property described herein for a frequency synthesizer may also hold for any frequency synthesizer described herein. It will be understood that any property described herein for a specific method may also hold for any method described herein. Furthermore, it will be understood that for any frequency synthesizer or method described herein, not necessarily all the components or steps described must be enclosed in the device or method, but only some (but not all) components or steps may be enclosed.

[0029] In an embodiment, a "circuit" may be understood as any kind of a logic implementing entity, which may be special purpose circuitry or a processor executing software stored in a memory, firmware, or any combination thereof. Thus, in an embodiment, a "circuit" may be a hard-wired logic circuit or a programmable logic circuit such as a programmable processor, e.g. a microprocessor (e.g. a Complex Instruction Set Computer (CISC) processor or a Reduced Instruction Set Computer (RISC) processor). A "circuit" may also be a processor executing software, e.g. any kind of computer program, e.g. a computer program using a virtual machine code such as e.g. Java. Any other kind of implementation of the respective functions which will be described in more detail below may also be understood as a "circuit" in accordance with an alternative embodiment.

[0030] In the specification the term "comprising" shall be understood to have a broad meaning similar to the term "including" and will be understood to imply the inclusion of a stated integer or step or group of integers or steps but not the exclusion of any other integer or step or group of integers or steps. This definition also applies to variations on the term "comprising" such as "comprise" and "comprises".

[0031] The term "coupled" (or "connected") herein may be understood as electrically coupled or as mechanically coupled, for example attached or fixed, or just in contact without any fixation, and it will be understood that both direct coupling or indirect coupling (in other words: coupling without direct contact) may be provided.

[0032] In order that the invention may be readily understood and put into practical effect, particular embodiments will now be described by way of examples and not limitations, and with reference to the figures.

[0033] The requirements for local oscillator and clock systems in wireless and wireline applications are increasingly stringent as the standards continuously evolve. In addition, it is desirable to have the output frequency range as wide as possible in applications such as the software-defined radio. It is challenging to achieve low-jitter, i.e. low phase noise while keeping power consumption low. Frequency synthesizers based on multiplying delay-locked loop (MDLL) and injection-locked oscillator (ILO) are promising architectures in this aspect.

The MDLL is similar to the ring oscillator in which a signal traveling along the delay line is periodically replaced by a clean reference signal. As a result, the phase noise of the ring oscillator is high-filtered up to half of the reference frequency and the amount of jitter is significantly reduced. During the injection of the reference signal, the edge of the ring oscillator output is replaced or moved to the edge of the reference signal. Therefore, the edge of the reference signal should be aligned with the edge of the ring oscillator output. Any mismatch between the position of the edges of the reference signal and the edges of the ring oscillator output may increase the spur level or in some cases, cause the injection to fail. To avoid such mismatches, the frequency of the ring oscillator should be integer multiples of the reference frequency which may be difficult to implement in practical radiofrequency systems where high frequency resolution is required. Methods to resolve the abovementioned issues may include using multiphase signals of a ring oscillator or variable delay cells to synthesize fractional multiples of a reference frequency. However, using multiphase signals of the ring oscillator to synthesize fractional multiples of the reference frequency may require a large number of delay cells in the ring oscillator to achieve fine frequency resolution since the output frequency resolution is determined by the number of delay cells. Having a large number of delay cells may increase the area and power consumption. The fractional multiples of the reference signal may alternatively be synthesized using variable delay cells to delay the reference signal according to the error of a delta sigma modulator (DSM). This dynamically delayed reference signal may be aligned with the output of the oscillator even when the oscillator's output frequency is fractional multiples of the reference frequency. The dynamically delayed reference may also reduce the quantization noise of the DSM. However, this method requires the use of two independent delay cells and there may be a mismatch between the two delay cells such that the DSM noise may not be fully cancelled. In addition, the required dynamic range of the delay cell may depend on the output frequency, so it may be difficult to optimize the design over a wide output frequency range. Alternatively, Finite impulse response (FIR) filtering method may be used. However, filtering may not sufficiently suppress the quantization noise of the DSM. Moreover, since the FIR filter may be implemented by several on-chip capacitors, it may occupy a large area. Another method for synthesizing the fractional frequency may be to use adjustable delay cell and have the output frequency resolution determined by the least significant bit of the delay cell. However, the output frequency resolution may be very sensitive to process, voltage and temperature variation. The dynamic range requirement of the delay cell may also depend on the output frequency.

[0034] According to various embodiments, a frequency synthesizer may include a fractional reference frequency generator (FRFG), a digital calibration engine and a phase locked loop (PLL). The frequency synthesizer may be provided with a reference signal. In contrast to conventional injection-locking architectures, the frequency synthesizer may be capable of fractional-N frequency synthesis. The architecture of the frequency synthesizer may also be referred herein as a fractional-N injection-locking PLL architecture. The frequency synthesizer may synthesize frequency with a low jitter, i.e. low noise. The integrated root- mean-square (RMS) jitter may be as low as 2ps rms at output frequencies in a range of about 0.1 GHz to 4GHz. The regarding figure of merit may be about -239 at an output frequency of about 2GHz. [0035] According to various embodiments, the FRFG may be configured to generate a fractional multiple or division of the reference signal. The fractional multiple or division of the reference signal may be referred herein as a fractional frequency signal. The output of the FRFG may include noise. The FRFG may include modulator, for example, a delta-sigma modulator (DSM). The FRFG may also include a delay locked loop (DLL). The DLL may include a set of delay cells. The noise in the output of the FRFG may stem from quantization noise of the DSM and mismatches among the delay cells. The FRFG may further include a phase rotator for tuning the output frequency. The frequency tuning range may be doubled by using a bi-directional phase rotator. The DLL may alleviate the specification of the delay cell required for quantization noise compensation.

[0036] According to various embodiments, the digital calibration engine, also referred herein as digital compensation circuit or digital cancellation loops, may be configured to at least partially remove the noise in the output of the FRFG. The digital calibration engine may suppress or cancel the quantization noise of the DSM. The quantization noise of the DSM may be removed or suppressed using a digital correction method. The digital correction method may include applying least-mean-square (LMS) algorithm. The digital calibration engine may also reduce the impact of the mismatches among the delay cells, for example by calibrating the mismatches among the delay cells. An algorithm for calibrating the delay mismatches among the delay cells may be provided.

[0037] According to various embodiments, the dynamic range requirement for the delay cell may depend on the reference frequency instead of depending on the output frequency. As the reference frequency is rarely changed in a specific application, it may be easier to optimize the design of the delay cell for a wide output frequency range.

[0038] According to various embodiments, the architecture of the frequency synthesizer may be suitable for digital systems and therefore, may benefit from advances in semiconductor technology, for example may be implemented in complementary metal-oxide- semiconductor to save space and to lower power consumption.

[0039] According to various embodiments, the PLL may include a dual-loop architecture. The PLL may include an oscillator. The oscillator may be injection-locked to the fractional frequency signal. In other words, the PLL may be configured to generate an output signal whose phase is related to the phase of the fractional frequency signal. The dual-loop injection-locked PLL may be used to remove delay conflict between the reference signal and the PLL. [0040] FIG. 1 shows a flow diagram 100. The flow diagram 100 illustrates a method for synthesizing a frequency according to various embodiments. The method may include a plurality of steps. In step 104, a fractional frequency signal may be generated based on a reference signal, using a fractional frequency signal generator. The fractional frequency signal generator may include a delay-locked loop. The delay-locked loop may include a plurality of delay cells. In step 106, an oscillator may be locked to the fractional frequency signal, using a phase-locked loop circuit. The frequency of an output of the phase-locked loop circuit may be on average, at least substantially equal to a frequency of the fractional frequency signal. The frequency of the output of the phase-locked loop circuit may also be a non-integer multiple of a frequency of the fractional frequency signal. In step 108, the fractional noise may be removed from the fractional frequency signal with a compensation loop. In step 110, respective delay mismatches of the plurality of delay cells may be calibrated.

[0041] In other words, according to various embodiments, a reference signal may be provided. A fractional frequency signal generator having a delay-locked loop (DLL) may be used to generate a fractional frequency signal, based on the reference signal. The DLL may include more than one delay cell. An oscillator may be provided. The oscillator may be locked to the fractional frequency signal generated by the fractional frequency signal generator, using a phase-locked loop (PLL) circuit. The PLL circuit may also be referred herein simply as a PLL. The output of the PLL circuit may have a frequency that is at least substantially equal to an average frequency of the fractional frequency signal. Fractional noise may be removed from the fractional frequency signal using a compensation loop. The compensation loop may be part of a digital calibration engine or digital calibration circuit. Calibration may be performed on the respective delay mismatches of the plurality of delay cells of the DLL.

[0042] FIG. 2 shows a flow diagram 200. The flow diagram 200 illustrates a method for synthesizing a frequency according to various embodiments. The method illustrated in the flow diagram 200 may include steps 104, 106, 108 and 110 like the method illustrated in the flow diagram 100. The method illustrated in flow diagram 200 may further include steps 102,

112 and 114. In step 102, a modulator signal may be provided. The fractional signal generated in step 104 may be further generated based on the modulator signal. In step 112, an output frequency of the oscillator may be adjusted to a target frequency. The method may further include injecting the fractional frequency signal to a further oscillator. The further oscillator may be part of the PLL circuit. The output frequency of the further oscillator may be adjusted to the target frequency. In step 114, quantization noise from the fractional frequency signal may be removed: The quantization noise may be removed from the fractional frequency signal by adjusting a variable delay cell of the fractional frequency signal generator.

[0043] FIG. 3 shows a frequency synthesizer 300 according to various embodiments. The frequency synthesizer 300 may include a fractional frequency signal generator 304, a phase- locked loop (PLL) circuit 306 and a digital calibration circuit 308. The fractional frequency signal generator 304 may be configured to generate a fractional frequency signal based on a reference signal. The fractional frequency signal generator 304 may include a delay-locked loop (DLL). The DLL may include a plurality of delay cells. The PLL circuit 306 may be locked to the fractional frequency signal. The digital calibration circuit 308 may be configured to calibrate respective delay mismatches of the plurality of delay cells. A frequency of the fractional frequency signal may be on an average, at least substantially equal to a frequency of an output of the PLL circuit. The frequency synthesizer 300 may further include a modulator that is configured to generate a modulator signal. The modulator signal may be used in the process of generating the fractional frequency signal. The modulator may be a delta-sigma modulator (DSM). The frequency synthesizer 300 may further include a compensation loop configured to remove fractional noise from the fractional frequency signal.

[0044] FIG. 4 shows a timing diagram 400 illustrating the problems with using the conventional injection-locking technique in frequency synthesis. The timing diagram 400 includes a first reference signal 440, a first voltage-controlled oscillator (VCO) signal 442, a second reference signal 444 and a second voltage-controlled oscillator (VCO) signal 446. Accumulated noise on a VCO signal may be reduced by injection-locking the VCO signal to a clean reference signal. However, the injection- locking technique is only applicable when the frequency of the VCO signal, f _vco is an integer multiple of the frequency of the clean reference signal, f _REF for example as shown in the case of the first reference signal 440 and the first VCO signal 442. If f _vco is a fractional multiple of f _REF , for example as shown by the second reference signal 444 and the second VCO signal 446, the injection-locking may be degraded or may fail, because the edges of the reference signal cannot be aligned with the edges of the VCO signal. Therefore, the usefulness of the injection-locking technique may be limited in conventional frequency synthesizers. [0045] FIG. 5 shows a block diagram of a frequency synthesizer 500 according to various embodiments. The frequency synthesizer 500 may be identical or similar to the frequency synthesizer 300 of FIG. 3. The frequency synthesizer 500 may include a fractional-N injection-locked PLL circuit. The frequency synthesizer 500 may include a fractional reference frequency generator (FRFG) 504. The FRFG 504 may identical to, or similar to, the fractional frequency signal generator 304. The FRFG 504 may be used to generate a fractional frequency signal based on a reference signal. The frequency synthesizer 500 may further include a digital calibration circuit 508, also referred herein as a digital calibration engine. The digital calibration circuit 508 may be identical to, or similar to, the digital calibration circuit 308 and may also include a compensation loop configured to remove fractional noise from the fractional frequency. The frequency synthesizer 500 may further include a phase-locked loop (PLL) 506. The PLL 506 may be identical to, or similar to the PLL circuit 306.

[0046] The FRFG 504 may include a multiphase generation circuit 550, a phase rotator 554, a variable delay circuit 556 and a delta-sigma modulator (DSM) 558. The multiphase generation circuit 550 may include a delay-locked loop (DLL) 552 configured to generate multiphase signals based on an incoming reference signal provided by input 502. The multiphase signals may include a plurality of clock signals, wherein each clock signal is the reference signal time-shifted by a respective multiple of a delay period. For example, a first clock signal is the reference signal time-shifted by one delay period while a second clock signal is the reference signal time-shifted by two delay periods. The DLL 552 may include a plurality of delay cells. The multiphase generation circuit 550 may provide the generated multiphase signals to the phase rotator 554. The DSM 558 may receive an input, denoted as

DSMIN in the block diagram, and may provide a DSM output and a DSM error signal. The phase rotator may further receive the DSM output. The DSM output is denoted in the block diagram as DSM _O UT- The phase rotator 554 may be configured to select one of the edges from the output of the DLL, i.e. the multiphase signals, based on a rotating direction of the phase rotator 554. The phase rotator 554 may be configured to select one of the edges from the multiphase signals further based on based on the DSM output. The variable delay circuit

556 may receive the output of the phase rotator 554 and may be configured to delay an output of the phase rotator. The variable delay circuit 556 may be configured to generate a fractional frequency signal. The fractional frequency signal is indicated as Fref_frac in the block diagram. A period of the fractional frequency signal may be at least substantially in a range determined by a sum or a difference of a period of the reference signal and a multiple of a delay of a delay cell in the delay locked loop. The frequency of the fractional frequency signal may be dependent on the rotating direction of the phase rotator 554.

[0047] The digital calibration circuit 508 may be configured to compensate for the quantization noise of the DSM 558 and mismatches of delay cells in the DLL 552. The digital calibration circuit 508 may include a mismatch calibration circuit 562 and a noise cancellation circuit 560. The noise cancellation circuit 560 may receive the DSM error signal from the DSM 558. The noise cancellation circuit 560 may provide an output to the variable delay circuit 556. The noise cancellation circuit may be configured to remove quantization noise of the DSM 558. The mismatch calibration circuit 562 may calibrate respective delay mismatches of the plurality of delay cells of the DLL 552. The calibration of mismatches may include extracting the respective delay mismatches between delay cells of the DLL using a time-to-digital converter (TDC). The delay of a respective delay cell may be adjusted based on the extracted respective delay mismatch.

[0048] The PLL 506 may have a dual-loop injection-locked PLL architecture. The PLL 506 may include a first voltage-controlled oscillator (VCO) 572, a loop filter 574, a divider 576 and a second VCO 578. The PLL 506 may include a first oscillator, i.e. first VCO 572 in a feedback loop. The PLL 506 may further include a compensation loop configured to remove fractional noise from the fractional frequency signal. The PLL 506 may further include a second oscillator, i.e. the second VCO 578 that is injection-locked with the fractional frequency signal. The second VCO 578 may be outside of the feedback loop. This injection method may avoid the conflict between the delay of the reference signal and that of the PLL 506. The PLL 506 may further include a low-pass filter (LPF) 580. The second VCO 578 may be identical to the first VCO 572. The output frequency of both the first VCO 572 and the second VCO 578 may be adjusted to the target frequency. Each of the first VCO 572 and the second VCO 578 may be configured to generate an output signal having a target frequency. The PLL 506 may receive the fractional frequency signal provided by the variable delay circuit 556.

[0049] FIG. 6 shows a block diagram 600 of the FRFG 504. The period of the phase rotator output is indicated as T _PR . T _PR may be expressed as T _PR = T _R + α · T _d where a is the normalized modulator output, i.e. normalized DSM output. When the rotating direction of the phase rotator 554 is incremental and the DSM output is high (a = 1), T _PR becomes T + T _d , where T _R is the period of the reference signal and T _d is the delay of the delay cell in the DLL

552. As a result, the available frequency at the phase rotator output may range from to

^T R+ ^T d — , depending on the amount of rotation of the phase rotator 554 in the incremental direction.

TR

In order to increase the frequency range, the rotating direction of the phase rotator 554 may be reversed so that T _PR = T _R — a · T _d . T _PR becomes T _R — T _d when the DSM output is high.

1 1

The available frequency at the output of the phase rotator 554 may range from— to ,

^T R T _R -T _D depending on the amount of rotation of the phase rotator in the reverse direction. Therefore, the phase rotator 554 may be able to tune frequency in a range of to

R + CL T _R -T _D

[0050] FIG. 7 shows a timing diagram 700 of the phase rotator 554 when the phase rotator 554 has a normal rotating direction, assuming that the DLL has six delay cells.

[0051] FIG. 8 shows a timing diagram 800 of the phase rotator 554 when the phase rotator 554 has a reversed rotating direction. Combining the normal rotating direction and the reversed rotating direction, the overall output frequency of the phase rotator 554 may range

1 1

from to . The output of the phase rotator 554 may be used as the reference clock

TR +T(1 TR-Td

of the injection-locked PLL 506.

[0052] FIG. 9 shows a block diagram 900 showing part of the F FG 504, the noise cancellation circuit 560 and part of the PLL 506. FIG. 9 shows digital cancellation of the noise. The DSM-modulated output period of the phase rotator 554 may include a large amount of quantization noise. The quantization noise should be cancelled since the output of the phase rotator 554 may be used as the reference clock of the injection-locked PLL 506. The output period of the phase rotator 554, T _PR is T _t + q[n] where T _t is the expected output period and q [n] is the quantization noise of the DSM 558. Since the PLL 506 is locked to the average frequency of its reference signal which is the frequency of the output of the phase rotator 554, the output period of the divider may eventually be equal to 7^. The output of the phase frequency detector (PFD) 582 may represent the quantization noise i.e. q[ri], added by the DSM 558. The residue of the quantization noise may be detected at the output of PFD 582. The correlation between q[n] and the error from the DSM 558 may be calculated and the resulting output may be used to update the gain of the compensation controlling input of the variable delay circuit 556. This may be an implementation of the least-mean square (LMS) algorithm. The LSM algorithm may adjust the delay of the variable delay circuit 556 to suppress the quantization noise of the DSM 558. After the calibration loop is settled, the output period of the variable delay circuit 556 may converge to Γ _έ . The variable delay circuit 556 may also be referred herein as a variable delay cell. [0053] FIG. 10 shows a timing diagram 1000 of the output of the phase rotator 554 and the output of the calibrated signal, TCAL with mismatch among the delay cells 1010 in the DLL 552. The timing diagram 1000 includes an output signal of the phase rotator 554, indicated as OUT _PR 1002. The timing diagram 1000 also includes an output signal of the DSM 558, indicated as DSM _0UT 1004. The period of the phase rotator 554 is indicated as T _PR 1006. The calibrated output is indicated as OUT _CAL 1008. The period of the calibrated output is indicated as T _CAL 1012. The output of the time-to-digital converter (TDC) is indicated as tdc[n]— tdc[n— 1] 1014. The modulator output a is indicated as "a" in the TDC output in the timing diagram 1000. The LMS algorithm may function correctly when there are no delay mismatches among the delay cells 1010 in the DLL 552. If there are delay mismatches, the quantization noise may not be cancelled perfectly. Moreover, the noise may be folded into low frequencies, thereby degrading the output of the phase rotator 554 significantly. The timing diagram 1000 assumes that there are delay mismatches in the DLL 552. t _d0 to t _dn _ represent the delay of the delay cell 1010 in the DLL 552. Ideally, all of the delay cells 1010 should be identical. The output of the phase rotator 554 may be modulated by the output of the DSM 558. Each delay of the delay cell 1010 may be added sequentially. For example, when the DSM _0UT 1004 is high, OUT _PR 1002 may be equal to T _R + t _d0 and when there is another high signal level from the DSM 558, 0UT _PR 1002 may be T _R + t _dl . After calibration, O UT _CAL 1008 may be T _T + at _dQ and T _T + at _dl resulting from residual quantization noise, at _d0 and t _dl . If there is no mismatch, 0UT _PR 1002 will be equal to Tj. Tj may be expressed as TR = T _R x (1 + · tdl) while T _R may be expressed as T _R =∑ ₌₀ tdi.

[0054] FIG. 11 shows a block diagram 1100 of the digital calibration for mismatches in the DLL 552. In order to remove the residual quantization noise introduced by the mismatches of the delay cell 1010, an additional digital calibration loop, i.e. the mismatch calibration circuit 562, may be introduced. The mismatch of the delay cell 1010 may be extracted by the time- to-digital converter (TDC) and differentiator which follow the TDC output. This extraction may be enabled only when the output of the DSM 558 is high. The output of the differentiator may then be categorized according to the target delay cell and may be the input of the LPF. The output of the LPF may be accumulated and the resulting output may adjust the delay of the delay cell 1010. The calibration may be activated until the inputs of all the LPFs are close to zero and then it may be deactivated to reduce power consumption.

[0055] In the following, a behavior simulation of a method for synthesizing a frequency according to various embodiments will be described. The performance of the frequency synthesizer is verified by using a behavior simulator written in Python. The simulated frequency synthesizer is identical to or similar to the frequency synthesizer 300 or 500.

[0056] As it is difficult to simulate the injection-locking of the PLL circuit 306, the phase noise at the output of the fractional frequency signal generator 304 is calculated. When the injection oscillator is locked, the phase noise is set by synchronizing it to the reference signal within the locked range. Since the injection-locking phenomenon is not easy to verify during the behavior simulation, the simulation is focused on evaluating the phase noise of the input of the injection-locked PLL circuit 306.

[0057] FIG. 12 shows a graph 1200 showing the simulated phase noise of a frequency synthesizer in an ideal situation without any delay mismatches in the DLL. The simulation assumes a 100MHz reference signal and a 10-stage DLL are provided. Each delay cell in the DLL is assumed to have a Ins delay. The graph 1200 includes a horizontal axis 1202 indicating frequency offset measured in hertz (Hz) and a vertical axis 1204 indicating phase noise measured in decibels relative to the carrier per hertz (dBc/Hz). The phase noise of the reference signal is plotted in a first plot 1220. The phase noise of the phase rotator output is plotted in a second plot 1222. As expected, the output of the phase rotator contains large amount of quantization noise. The phase noise of the calibrated signal is plotted in a third plot 1224. Since the quantization noise of the DSM is cancelled by the LMS algorithm, the noise level of the calibrated signal is almost the same as the phase noise of the reference signal.

[0058] FIG. 13 shows a graph 1300 showing the simulated phase noise of a frequency synthesizer, with delay mismatches in the delay cells. Similar to the graph 1200, the simulation assumes a 100MHz reference signal and a 10-stage DLL are provided. The graph 1300 includes a horizontal axis 1302 indicating frequency offset measured in Hz and a vertical axis 1304 indicating phase noise measured in dBc/Hz. Random delay mismatches are added to the delay cells with 10ps _m s standard deviation. The delay mismatches of 10ps _m s correspond to 1% of its nominal delay. A first plot 1330 shows the phase noise of the reference signal. A second plot 1332 shows the phase noise of the phase rotator output. A third plot 1334 shows the phase noise of the calibrated signal. The mismatches increase the noise level even after the calibration is performed. In addition, the noise performance at low offset frequencies is degraded due to the folding effect.

[0059] FIG. 14 shows a graph 1400 showing the control input signal, in other words, control words of the delay cells after the calibration is enabled. The delay mismatch calibration may have finite bit- width. The graph 1400 includes a horizontal axis 1402 indicating the number of cycles and a vertical axis 1404 indicating control input for delay cell. The graph 1400 includes a plurality of plots, each plot of the plurality of plots indicating the control input for a respective delay cell. In order to reduce the degradation introduced by the mismatches, the digital calibration path is enabled. The delay cells are controlled by the digital calibration individually. Each delay cell may be finely controlled to reduce the mismatches. After the mismatch calibration is turned on, the calibration adjusts the control input of the delay cell and the delay of the delay cell converges to its ideal value, Ins. Then, the digital calibration is deactivated, to minimize the power consumption without comprising performance. The resulting phase noise is plotted in FIG. 16.

[0060] FIG. 15 shows a graph 1500 showing the delay of the delay cells after the calibration is enabled. The graph 1500 includes a horizontal axis 1502 indicating the number of cycles and a vertical axis 1504 indicating delay of a delay cell. The graph 1500 includes a plurality of plots, each plot of the plurality of plots indicating the delay of a respective delay cell.

[0061] FIG. 16 shows a graph 1600 showing the resulting phase noise after the calibration described in relation to FIG. 14 is performed. The simulation assumes a reference frequency of 100 MHz and that the DLL is a 10-stage DLL with a time delay of Ins. Delay mismatches of about lOpsrms, i.e. 1% of the nominal delay of the DLL, were added. The delay mismatches were then calibrated. Digital quantization noise was added. The VCO noise was about -HOdBc/Hz at lMHz. The delay cell noise is also included in the simulation. The graph 1600 includes a horizontal axis 1602 indicating frequency offset measured in Hz and a vertical axis 1604 indicating phase noise measured in dBc/Hz. A first plot 1660 shows the phase noise of the reference signal. A second plot 1662 shows the phase noise of the phase rotator output. A third plot 1664 shows the phase noise of the calibrated signal. The noise floor of the delay cell is assumed to be -160dBc/Hz. The l/f corner frequency is assumed to be 100 kHz.

[0062] FIG. 17 shows a graph 1700 showing the relationship between phase noise and frequency. The graph 1700 includes a horizontal axis 1702 indicating frequency measured in

Hz and a vertical axis 1704 indicating phase noise measured in dBc/Hz. The graph 1700 includes a plot 1770 indicating the relationship between frequency and phase noise.

[0063] FIG. 18 shows a graph 1800 showing the relationship between phase noise and frequency. The graph 1800 includes a horizontal axis 1802 indicating frequency measured in

Hz and a vertical axis 1804 indicating phase noise measured in dBc/Hz. The graph 1800 includes a first plot 1880 indicating the variation of phase noise with frequency for one delay cell. A second plot 1882 shows the variation of phase noise with frequency after 10 delay cells. The graph 1800 shows that the phase noise after 10 delay cells (second plot 1882) is about lOdB larger than the phase noise after one delay cell (first plot 1880), which is theoretically correct. The delay cell is assumed to be a simple inverter-based delay cell.

[0064] FIG. 19 shows a table 1900 summarizing the jitter measured in the simulation, for various values of the injection strength 1990 and at various frequencies.

[0065] According to various embodiments, a frequency synthesizer including a fractional-N injection-locked PLL can achieve the finest frequency resolution with better jitter performance as compared to existing frequency synthesizers. The frequency resolution achieved may be less than 0.1 kHz, while the integrated rms jitter may be about 0.6 ps at 2GHz taking into account a practical delay cell's noise and other non-idealities. The area of the frequency synthesizer may be as small as 0.2mm ² . The output frequency may be at least substantially in a range of 0.1 GHz to 4GHz. The power consumption may be about 3mW.

[0066] While embodiments of the invention have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced. It will be appreciated that common numerals, used in the relevant drawings, refer to components that serve a similar or the same purpose.