A FULL BRIDGE CIRCUIT

This invention relates to a circuit configuration known as a full bridge circuit.

The basic design of such a circuit is extremely well known. A full bridge is used to convert a DC supply to AC to drive a load.

One known form of such a circuit is shown in Figure 1.

In Figure 1 four switching devices TRl ₅ TR2, TR3, TR4 are shown connected in a conventional bridge circuit 10. TRl, TR2, TR3 and TR4 are, as shown, field- effect transistor ("FET") devices. Usually FET transistors are considered most suitable for this duty as they are available with high voltage and current ratings, and switch from the "off" (open circuit) state to the "on" (conductive state) quickly; One characteristic of a typical FET device is the unavoidable inclusion of a diode formed as part of the construction. This diode electrically appears in parallel with the FET switching element. Often the diode is of no consequence as the circuit reverse biases the diode, and it never conducts.

In this circuit one may consider the switching devices TR2, TR3 as a first pair of such devices, and the switching devices TRl, TR4 as a second pair of such devices.

Each respective switching device TRl, TR4 of the second pair is connected in series with, a respective switching device of the first pair.

Thus switching device TRl is connected in series with switching device TR2. Switching device TR4 is connected in series with switching device TR3.

The switching devices TRl ₅ TR2 constitute a first, switchable conducting path that is connected in parallel with a second, switchable, conducting path constituted by the series connection of the diodes TR4, TR3 of the respective pairs.

The switching devices TRl, TR2, TR3, TR4 axe arranged so as to be forwardly conducting in the directions as conventionally signified by their symbols used in Figure 1.

A load 11 is connected so as to bridge the aforesaid parallel conducting paths. Load 11 defines such a bridge at a location that is intermediate the two pairs of switching devices.

As is conventional, an inductor 12 is connected in series with the load 11 for the purpose of reducing, in a per se known manner, high frequency fluctuations resulting from known effects of the switching device switching action.

The inductor 12 typically is a component added in series with the load 11 for this purpose. In some other arrangements, however, one may consider the inductor 12 to be an inherent characteristic of the load device 11.

A gate driver 13 is operatively connected to each switching device TRl, TR2, TR3, TR4 as shown, for the purpose of switching the switching devices in a manner that is well known in the art.

During use of the circuit of Figure 1 a DC voltage is applied across the circuit terminals represented by numerals 14 and 16. In the arrangement shown, terminal 16 is designated as the ground ("GND").

"400 V" adjacent terminal 14 signifies a typical DC voltage that may be applied when the circuit of Figure 1 is used as part of an AC waveform power supply.

In the arrangement of Figure 1, the composite load represented by components 11 and 12 may be considered as terminated at either end at the connectors labelled L2 and Ll in Figure 1. These labels will be referred to in the remainder of the description.

In use of the Figure 1 circuit, during the positive half cycle when current is flowing from L2 to Ll, TR4 is switched on and TRl and TR2 are driven with a variable mark space ratio such that TRl and TR2 are never both on at the same time. The effective voltage across the load varies in proportion to the mark space ratio. When TRl is always on, no current flows through the load. When TR2 is always on, the full bridge DC supply voltage is presented across the load, and when the duty cycle is 50%, the effective voltage across the load corresponds to that which would flow with roughly half the DC supply voltage. By varying the mark space ratio suitably, the current through the load can be made to approximate a sinusoidal shape or any other desired waveform and the amplitude of that waveform can be varied by adjusting the peak mark space ratio.

The negative half cycle of the waveform can be generated in a similar manner but with TR4 off and TR3 on, in a manner known to those of skill in the art.

A disadvantage of the Figure 1 circuit is that in an attempt to avoid the undesirable condition where TRl and TR2 are on simultaneously, a delay is introduced so that TRl has time to turn off before TR2 turns on and vice versa. A typical delay might be of the order of one or several microseconds. However, during the period that both TRl and TR2 are off, the current that was flowing in the inductor has to flow through another path, namely the parasitic diode which is formed as part of the construction of the FET devices shown.

For example if current is flowing through TRl, and TRl is turned off in preparation for the control circuit to turn on TR2, the current then flows via TRl parasitic diode. Usually the unintentional but unavoidable parasitic diode integral with the FET is relatively slow to turn off when the voltage across it is reversed.

This means that for a short period of time, typically a fraction of a microsecond, the diode inside TRl is conducting and TR2 is turned on leading to a near short circuit across the DC supply. For a fraction of a microsecond, a high current flows in TRl and TR2 until the diode in TRl re-establishes reversed biased

(blocking) condition from the forward (current carrying) condition. A similar

effect occurs during the reverse changeover when TR2 is turned off and TRl starts to turn on.

This current is undesirable as it causes large high frequency currents to flow, generating electrical interference, heating up TRl and TR2, and wasting energy that had been intended to be delivered to the load.

A similar effect can occur in devices TR3 and TR4 but this is generally less troublesome, both because the switching frequency is often much lower, so the effect occurs less often, and because the circuit currents through the load are usually low when TR3 and TR4 switch over.

Various modifications to this circuit are possible but undesirably they generally increase complexity and cost and result in additional power losses.

One popular option is to replace the FET's with insulated gate bipolar transistor ("IGBT") devices. These do not have the parasitic diode, but are usually slower to switch from one state to the other and particularly from the on to the off state. During this transitional period, the IGBT dissipates significant power which again wastes energy and causes undesirable heating of circuit components.

According to the invention in a first aspect there is provided a full bridge circuit comprising first and second pairs of parallel connected, one-way switchable switching devices, each respective said switching device of the second pair being connected in series with a respective said switching device of the first said pair to define two switchable parallel conducting paths, a load being connected so as to bridge the parallel conducting paths between the said switching devices of the first pair and the said switching devices of the second pair, and the circuit being connectable so as to apply an alternating current selectively to flow in parts of the parallel conducting paths, characterised in that the switching devices of the first pair are FET devices; and the switching devices of the second pair are IGBT devices.

Conveniently the circuit of the invention includes one or more gate drivers for driving the gate terminals of the switching devices so as selectively to switch the switching devices on and off.

In a preferred embodiment of the invention one or more of the gate drivers selectively switches the switching devices defining one of the said parallel conducting paths at a time according to a variable mark space ratio sequence.

Conveniently one or more of the said gate drivers switches the switching devices, of the first and second pairs that define one of the said parallel conducting paths, such that the switching devices of the said conducting path are never simultaneously forwardly conducting.

It is also preferred that one or more of the said gate drivers selectively adjusts the peak mark space ratio applied to the switching devices of a said conducting path, whereby to adjust the amplitude of the waveform applied to the load.

Conveniently the circuit includes an inductor connected in series with the load.

Advantages of circuits in accordance with the invention are set out hereinbelow.

There now follows a description of a preferred embodiment of the invention, by way of non-limiting example, with reference being made to the accompanying drawings in which: Figure 1 is a schematic representation of a prior art, switched, full bridge circuit; and

Figure 2 is a schematic representation of a switched, full bridge circuit according to the invention.

As is evident from Figure 2, a circuit 10 according to the invention is very similar in configuration to the prior art circuit of Figure 1. The primary difference between the circuits of Figures 1 and 2 is that in Figure 1 all four switching

devices TRl, TR2, TR3, TR4 are FET devices. In contrast in Figure 2 the switching devices TRl and TR4 are IGBT transistors.

In view of the similarities between the Figure 1 and Figure 2 circuits, the following description refers principally to the effects of using IGBT' s as the switching devices TRl and TR4. Thus the reader of skill in the art would understand that the basic bridge principles described hereinabove in relation to Figure 1 apply in relation to the Figure 2 circuit.

In the Figure 2 circuit TRl and TR4 (IGBT) switch at the lower frequency, while TR2 or TR3 (FET) as desired are modulated on with a variable duty cycle to control the effective voltage across the load. IGBT switching devices do not have a parasitic diode. In practice manufacturers sometimes add a diode inside the same packaged circuit element as shown in the example above. Instead of the diode being slow, inherent and unavoidable, as with FETs ₅ the IGBT diode is specially designed for rapid recovery from the forward (current carrying) condition to the reversed biased (blocking) condition. If the IGBT chosen does not have an internal diode, a suitable external diode can be readily added during construction of the Figure 2 circuit.

In the context of diodes it should be noted that the term "fast" refers to the ability of a diode to shut off current flow very quicldy, perhaps in order of tens of nanoseconds, after the voltage across the diode reverses from a polarity which equates to the diode being forward biased and conducting, to the condition where the diode is reversed biased and conventionally regarded as non conducting. Conversely the term "slow" refers to a diode where the essential cessation of current flow under the condition described may take a significant fraction of a microsecond or even longer to occur.

In the preferred circuit according to the invention, during the positive half cycle when current is to flowing from L2 to Ll, TR4 is switched on and TR2 is driven with a variable mark space ratio. The effective voltage across the load varies in proportion to the mark space ratio.

When TR2 is always off, no current flows through the load, and when TR2 is always on the full bridge DC supply voltage is presented across the load. When the duty cycle is 50%, the current through the load corresponds to that which would flow with roughly half the DC supply voltage. By varying the mark space ratio suitably, the current through the load can be made to approximate a sinusoidal shape or any other desirable waveform and the amplitude of that waveform can be varied by adjusting the peak mark space ratio.

During the mark space modulation switching, when TR2 is off, the current that was flowing in the inductor continues to flow via the diode in parallel with TRl, circulating in a clockwise direction through TR4, load 11, inductor 12 and TRl. When TR2 is on, the diode inside or in parallel with TRl recovers rapidly resulting in much, less wasted power inside TR2 than in the case of the prior art circuit.

The FETs used in position TR2 and TR3 switch faster than IGBT devices, so their switching losses are less. Typically, in a bridge circuit designed to generate an AC waveform in the range of tens of Hz to hundreds of Hz these switch at a speed in the range of kHz to hundreds of kHz. The IGBT devices used in positions TRl and TR4 have higher switching losses, but as their switching rate is hundreds of times lower than that of the FET' s, a switching loss of several times or even 10 times the switching loss of the FET' s is acceptable and has limited impact on the overall circuit efficiency and losses. Also, the slow speed switching tends to occur when the load current is relatively low which also minimises losses when the IGBT's switch.

The negative half cycle of the waveform can be generated in a similar manner but with TR4 off and TRl on, and TR3 being modulated on/off to generate the desired waveshape.

The configuration of the invention improves efficiency, and requires only slow speed drive to the upper devices TRl and TR4, which cannot share a common

ground. TR2 and TR3 share a ground and it is generally easier and less expensive to implement high speed gate drives which are ground referenced.

Although as signified in Figure 2 the circuit of the invention is preferably intended to receive a DC voltage amplitude of 400 volts, being a typical amplitude of a DC supply derived from common single phase mains supply voltages via a piσwer factor correction circuit, the circuit of the invention may readily be configured to operate at other DC supply voltages. The precise choices of the FET and IGBT components needed to achieve such alteration of the circuit will occur to those of skill in the art. The invention as claimed is intended to embrace all such variants as would occur to such a worker.