Title:
GATE DRIVING CIRCUIT AND DISPLAY PANEL
Document Type and Number:
WIPO Patent Application WO/2022/077724
Kind Code:
A1
Abstract:
A gate driving circuit (00) and a display panel. A cycle of a clock signal is (a*T), and a duty cycle thereof is (T-2)/(2*T). A delay time between two adjacent stages of clock signals is a. A falling edge and a rising edge of a signal of a first input end (301) of a first pull-down module respectively pull down a signal of a first output end (302) and a signal of a second output end (303). If k％M is an odd number, a kth-stage gate signal line (20k) is connected to the first output end (302), and the corresponding first input end is connected to a (k％M)th-stage clock signal line.
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Inventors:
LIU YI (CN)
Application Number:
PCT/CN2020/132778
Publication Date:
April 21, 2022
Filing Date:
November 30, 2020
Export Citation:
Assignee:
TCL CHINA STAR OPTOELECTRONICS TECH CO LTD (CN)
International Classes:
G09G3/36
Foreign References:
| CN105529006A | 2016-04-27 | |||
| CN105355175A | 2016-02-24 | |||
| CN104517564A | 2015-04-15 | |||
| CN104517578A | 2015-04-15 | |||
| US20190147824A1 | 2019-05-16 |
Attorney, Agent or Firm:
PURPLEVINE INTELLECTUAL PROPERTY (SHENZHEN) CO., LTD. (CN)
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