The government of the United States of America has rights in this invention pursuant to contract No. awarded by the Department of the Air Force. _j ^"

TECHNICAL FIELD

_

This invention is related to charge transfer devices and, In particular, to gate modulation input circuits for infrared charge coupled device (CCD) imagers.

BACKGROUND OF THE INVENTION Infrared charge coupled device (CCD) imagers using gate modulation Input techniques Include a photo- sensitive detector controlling the potential on a CCD electrode overlying a charge coupled device channel. Modulation of the intensity of incident photons on the detector causes the potential of the CCD electrode to modulate accordingly, which modulates the current of injected carriers in the CCD channel passing beneath the modulated CCD electrode. The resulting modulated CCD current is the video signal representing the image viewed by the detector.

One problem with such devices is that the modu- lated CCD current must be superimposed upon a direct current (DC) (or "FAT ZERO") CCD current level so that

^• _U S^-TUTΞ SHEET »u*

large amplitude CCD output current modulations do not exceed the dynamic range of the CCD output device, as is well-known to those skilled in the art. The dynamic range of a CCD is determined by the difference between the noise level of the CCD output current (which establishes a minimum current level) and the maximum charge storing capacity of each unit cell (or "bucket") of the CCD (which establishes a maximum current level), in accordance with well-known principles in the art. Unfortunately, it Is not possible to provide a perfectly uniform DC current level to each of a plurality of CCD channels generating output signals from a planar array of photodetectors, due to well-known metal-insulator- • semiconductor processing non-uniformities. One solution to this problem Is to provide a high impedance DC current source for each CCD channel. However, such a solution Is not acceptable if the device is formed as a monolithic miniature integrated circuit because the resistor of the DC current source would consume too much space. This Is because a source impedance on the order of 10^° ohms Is required to guarantee uniform DC current levels between adjacent CCD channels. Further¬ more, such a solution is not acceptable because the signal gain between the detector output and the CCD output current would be reduced in proportion to the increase of the current source input impedance, thus decreasing the signal-to-nolse ratio in the CCD output current.

SUMMARY OF THE INVENTION

In the present invention, each CCD channel in a CCD focal plane array formed on a substrate has a high impedance DC current source comprising a polycrystalline silicon resistor formed monollthically in the substrate and having a resistance on the order of lO-^ ohms.

SUBSTITUTE SHEET

Such a high input impedance assures uniform DC current levels in all DC channels in the array regardless of processing non-uniformities. Unlike the resistive ele¬ ments of the prior art, the polycrystalline silicon resistor of this invention does not consume a large amount of space and therefore is compatible with the miniaturized monolithic integrated circuit structure disclosed herein.

Because of the small size of the polycrystalline silicon resistor used In this Invention, it Is possible to form a second polycrystalline silicon resistor in the monolithic integrated circuit as a load resistance for the photodetector in order to prevent the increase in input impedance in the CCD current source from reducing the signal gain in the CCD output. By increasing, the resistance of the polycrystalline silicon resistor utilized as the photodetector load resistance, the signal gain in the CCD output may actually be Increased.

DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified schematic diagram of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Charge coupled device imagers employing gate modulation are disclosed in The Infrared Handbook by the Infrared Information and Analysis Center, Environ¬ mental Research Institute of Michigan (1978) Library of Congress Catalog No. 77-90786, pages 12-27 through 12- 41, which is incorporated herein by reference. In particular, FIGS. 12-40 and 12-42 of The Infrared Handbook referenced above are schematic diagrams of CCD imager gate modulation circuits of the prior art. FIG. 12-42 (ibid) illustrates the concept of AC coupling of

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a CCD gate modulation input. Typically, a current source Is applied to the input diffusion so that a DC current level is constantly maintained In the CCD channel which may be modulated by the detector signal on the modulation gate connected to the detector output. Because of metal-Insulator-semlconductor processing non- uniformities well-known in the art, it is not possible to guarantee a uniform CCD transImpedance in each of a plurality of CCD channels in a focal plane array of detectors. Therefore, the DC current level may be non-uniform in the various channels. As a result, in most cases, some CCD channels In the array will be saturated with Injected charge while other CCD channels may be starved In response to a given input signal, causing severe distortion of the output video signal from the detector array. The problem of non-uniform DC current levels may be solved by increasing the Input impedance, through which a voltage Is applied to the Input diffusion, to be on the order of 10-*-^ ohns. Such a resistive element is of excessive size, and unacceptably reduces the device density of the array. (It should be noted, however, that such a solution may be acceptable in a discrete device such as that illustrated in FIG. 12-40 (ibid) In which device density is not critical.) Referring to the invention illustrated in the schematic diagram of FIG. 1 of the accompanying drawing, a CCD gate modulation input circuit i Is formed in a focal plane array comprising a plurality of such circuits, la-ln, on a semiconductor substrate 2 (pre- ferably comprising silicon) with a charge coupled device (CCD) channel 2a. The charge coupled device channel 2a comprises a portion of the substrate 2 which underlies a plurality of clocked CCD electrodes 3 including a gate modulation electrode 3a. An Input diffusion 5 of a conductivity type opposite frcm that of the substrate 2 is formed in the substrate at the

beginning of the CCD channel 2a. A DC (or FAT ZERO) level of current is injected beneath the gate modulation electrode 3a from the Input diffusion 5 by means of a DC bias voltage source 7 connected through a high Input impedance 9 to Input diffusion 5« The high input

Impedance 9 comprises a polycrystalline silicon resistor formed in the semiconductor substrate 1 which is doped to have a resistance on the order of 1 x lO^O ohms. The high resistance of the polycrystalline silicon resistor guarantees that the DC level of current injected from the input diffusion 5 beneath the modula¬ tion gate electrode 3a will be uniform between adjacent CCD channels (not shown) despite the CCD transimpedance ; non-uniformities. An indium doped silicon detector 11 (of the same class of detectors so those disclosed in The Infrared Handbook referenced above at pages 11-13 through 11-98) is formed on the substrate 1. It is biased by a bias voltage source 13 and has Its output connected through a coupling capacitor 15 to the electrode 3a in the manner of AC coupled gate modulation illustrated in The Infrared Handbook referenced above at FIG. 12-42. A reset MOSFET 17 periodically resets the potential of the gate modulation electrode 3a to that of a reset voltage source 18.

The gain of the signal represented by the CCD output current flowing in the CCD channel 2a is increased by providing a second polycrystalline silicon resistor 19 connected between the output of the detector 11 and ground. It will be recognized by those skilled in the art that the gain between the detector output current and the CCD output current is proportional to the resistance RL of the polycrystalline silicon load resistor 19, divided by the resistance R _$ of the poly- crystalline silicon source resistor 9 - Since a gain on

the order of 2 Is preferred, the resistance of the poly¬ crystalline silicon load resistor 19 is selected so that R _L = 2 x 10 ¹⁰ ohms and R _s = 1 x 10 ¹⁰ ohms.

In addition to controlling the signal gain of the device, the polycrystalline silicon load resistor 19 has the additional advantage of rendering the gain of the device independent of processing non-uniformities. Specifically, the gain between the detector output and the CCD output current of the device of FIG. 1 is the ratio of the resistances of the resistors 9 , 19•

Because these resistors are located adjacent one another on the same semiconductive substrate, the gain ratio R/Rs is -easily controlled during fabrication and will therefore be uniform for a plurality of CCD channels (not shown) located on a focal plane array formed on the semiconductive substrate 1.

In summary, the polycrystalline silicon resistor 9 provides an extremely high input impedance, guaran¬ teeing that the dc current level Injected into the plurality of charge coupled devices of the type illustrated in FIG. 1 located on the same semicon¬ ductive substrate will be uniform despite processing non-uniformities. The polycrystalline silicon resistor 19 provides an extremely high load impedance for the detector 11 so that the gain between the CCD output current and the photodetector response may be selected In accordance with the resistances of the resistors , 19 thus providing sufficiently high gain to reduce the significance of CCD noise in the output signal and rendering the gain ratio of each device 1 in an array of such devices la-ln independent of processing non-uniformities.

In another embodiment of the Invention, the output of the detector 11 may be connected directly to the gate modulation electrode 3a (as indicated in dashed

SUBSTITUTE SHEET

line) while the coupling capacitor 15 and the reset MOSFET 16 may be eliminated if AC coupling is not necessary. AC coupling may not be necessary, for example, if background radiation Incident upon the detector 11 is of a constant intensity.

In the preferred embodiment of the invention, the voltage source 7 is selected in a manner well-known to those skilled in the art so that the modulation of the signal generated by the detector 11 and superimposed on the DC current level flowing in the CCD does not exceed the dynamic range of the CCD. The bias voltage source 13 of the indium doped silicon detector 11 is preferably on the order of -40 volts. The reset voltage source 18 ^■ may be on the order of 2 volts. Alternatively, the detector 11 may be of any type, either Intrinsic or extrinsic, disclosed in The Infrared Handbook referenced above between pages 11-13 and 11-98. Furthermore, the gate modulation electrode 3a need not necessarily overlie a charge coulped device but instead may overlie any type of charge transfer device.

Fabrication of polycrystalline silicon resistors is well known in the art, in accordance with the following references, the disclosures of which are Incorporated herein by reference:

Korsch et al, "Conduction Properties of Lightly Doped, Polycrystalline Silicon," Solid State Electronics, Vol. 21, pp. 1045-1051 (1978);

Seto, "The Electrical Properties of Polycrystalline Silicon Films," Journal of Applied Physics, Vol. 46, No. 12, pp. 5247 et seq. (Dec. 1975);

Andrews, "Electrical Conduction in Implanted Poly¬ crystalline Silicon," Journal of Electronic Materials, Vol. 8, No. 3 - PP. 227-290 (1979);

SUBSTITUTE SHEET

Seto, "Annealing Characteristics of Boron and

•Phosphorous Implanted Polycrystalline Silicon," Journal of Applied Physics, Vol. 47, No. 12, pp. 5167 et seq. (Dec. 1976); Mandurah, "Arsenic Segregation in Polycrystalline

Silicon," Applied Physics Letters, Vol. 36, No. 8, pp. 683 et seq. (15 April 1980);

Yaron, "Characteristics of Phosphorous Implanted Low Pressure Chemical Vapor Deposited Polycrystalline Silicon," Solid State Electronics, Vol. 22, pp. 1017-

1023 (1979); and

Gerzberg, "A Quantitative Model of the Effect of Grain Size on the Resistivity of Polycrystalline Silicon Resistors," IEE Electron Device Letters, Vol. ΞDL-4, No. 3, p. 38 et seq. (March 1980).

SUBSTITUTE SHEET