Title:
GENERATING DEVICE, GENERATING METHOD, AND PROGRAM
Document Type and Number:
WIPO Patent Application WO/2010/021233
Kind Code:
A1
Abstract:
The objectives are to reduce the launch transition and eventually the risk of yield loss even with few indefinite value (don’t care) bits within the input bits, such as in the case of test compression, without affecting the amount of test data, the failure detection rate, performance, or circuit design even with real speed scan testing while observing the internal signal lines, as well as to enable reduced power consumption in testing. A converting device (1) is provided with a specific internal signal line extracting unit (3), a specific internal signal line differentiating unit (5), a specifying unit (7) that specifies indefinite input value bits and input logic bits in the input bits, and an assignment unit (9) that assigns a logical value 1 or a logical value 0 to indefinite value bits in the input bits containing the specified indefinite input value bits. The specifying unit (7) is provided with an indefinite input value bit specifying unit (11) and an input logic bit specifying unit (13).
Inventors:
MIYASE KOHEI (JP)
WEN XIAOQING (JP)
KAJIHARA SEIJI (JP)
YAMATO YUTA (JP)
WEN XIAOQING (JP)
KAJIHARA SEIJI (JP)
YAMATO YUTA (JP)
Application Number:
PCT/JP2009/063586
Publication Date:
February 25, 2010
Filing Date:
July 30, 2009
Export Citation:
Assignee:
NAT UNIVERSITY CORP KYUSHU I O (JP)
MIYASE KOHEI (JP)
WEN XIAOQING (JP)
KAJIHARA SEIJI (JP)
YAMATO YUTA (JP)
MIYASE KOHEI (JP)
WEN XIAOQING (JP)
KAJIHARA SEIJI (JP)
YAMATO YUTA (JP)
International Classes:
G01R31/3183; G01R31/28; G06F11/22
Domestic Patent References:
| WO2008001818A1 | 2008-01-03 |
Foreign References:
| JP2007155339A | 2007-06-21 | |||
| JP2006047013A | 2006-02-16 |
Other References:
SEIJI KAJIHARA ET AL.: "Test Data Compression Using Don't-Care Identification and Statistical Encoding", PROCEEDINGS OF THE 11TH ASIAN TEST SYMPOSIUM (ATS'02), - 2002, pages 67 - 72
XIAOQING WEN ET AL.: "A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing", IEEE INTERNATIONAL TEST CONFERENCE ITC 2007, - October 2007 (2007-10-01), pages 1 - 10
H. FURUKAWA ET AL: "CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing", 17TH ASIAN TEST SYMPOSIUM ATS'08, - November 2008 (2008-11-01), pages 397 - 402
XIAOQING WEN ET AL.: "A Novel Scheme to Reduce Power Supply Noise for High-Quality At-Speed Scan Testing", IEEE INTERNATIONAL TEST CONFERENCE ITC 2007, - October 2007 (2007-10-01), pages 1 - 10
H. FURUKAWA ET AL: "CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing", 17TH ASIAN TEST SYMPOSIUM ATS'08, - November 2008 (2008-11-01), pages 397 - 402
Attorney, Agent or Firm:
HADATE Koji (JP)
Hadachi Koji (JP)
Hadachi Koji (JP)
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