GROUP DELAY ADJUSTMENT CIRCUIT, GROUP DELAY ADJUSTMENT SYSTEM, AND GROUP DELAY ADJUSTMENT METHOD

WIPO Patent Application WO/2005/104364

A1

A group delay adjustment circuit, a group delay adjustment system, and a group delay adjustment method capable of inclining the group delay difference without deteriorating the frequency band of an amplifying section and controlling the group delay difference to a constant level through external control. The group delay adjustment circuit (41) is characterized by comprising a first capacitor (21) connected with an input terminal (IN), a second capacitor (22) connected between the first capacitor (21) and an output terminal (OUT), and an impedance varying section (23) connected between the connection node of the first and second capacitors (21, 22) and the GND, having an adjustment terminal (24) and a monitor terminal (25), and capable of outputting a monitor signal corresponding to the group delay difference from the monitor terminal (25) by varying the impedance depending on a signal fed to the adjustment terminal (24) and thereby adjusting the group delay difference of the signal transmitted from the input terminal (IN) to the output terminal (OUT).

JPH01291512	ACTIVE FILTER CIRCUIT
JP2000082937	TIME DIVISION ANALOG FILTER CONTROL METHOD AND MAGNETIC DISK SYSTEM
JP4443424	Analog filter circuit

OHASHI NAOMI
ASANO HIROAKI

PCT/JP2005/004544

November 03, 2005

March 15, 2005

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MATSUSHITA ELECTRIC IND CO LTD (JP)
OHASHI NAOMI
ASANO HIROAKI

H03H11/04; H03H11/26; H03H11/46; (IPC1-7): H03H11/04; H03H11/26; H03H11/46

JPH03242014A	1991-10-29
JPS63114505U	1988-07-23
JPS5768916A	1982-04-27
JPH06310969A	1994-11-04

Takamatsu, Takeshi (7-13 Nishi-Shimbashi, 1-chom, Minato-ku Tokyo 03, JP)

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